• Journal of the Semiconductor & Display Technology
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• v.7 no.2
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• pp.23-27
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• 2008

Recently, regulation for THD (Total Harmonic Distortion) such as IEC 61000-3-2, IEEE 519 is being reinforced about a product which directly connects to AC line in order to prevent distortion of common power source in electronic equipment and electrical machinery. In order to satisfy these regulations, conventional circuits were used two-stage structure attached power factor correction circuit at ahead of converter but this method complicate the circuit and then a number of element increases thereupon the cost of production rises. in this paper, we propose a high efficiency single-stage 300W PFC fly-back converter that improved power factor and efficiency than conventional two-stage power module.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.279-281
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• 1996

This paper deals with the two stage surge protection device by using varistor and LC low pass filter. Recently varistor alone has been used with overvoltage protection devices for the AC power mains and has same problems associated with high remnant voltage and noise. In this work, in order to improve the cutoff performance of surge protection device, the lightning surge protection device having two stage hybrid circuit for an AC single phase mains was designed and fabricated. Operation characteristics and surge clamping performance of the surge protection device in an $8/20{\mu}s$ surge current are investigated. As a consequence, it is found that the proposed two stage surge protective device for AC power mains has a variety of advantages such as a smaller clamping voltage, high frequency noise reduction and large clamping capacity.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.535-538
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• 1994

In this paper, an isolated ZVS-PWM boost converter is proposed for single stage line conversion. For power factor correction, we used the half bridge topology at the primary side of isolation transformer permitting switching devices to operate under ZVS by using circuit parastics and operating at a fixed duty ratio near 50%. Thus the relatively continuous input current distortion and small size input filter are also achievable. The ZVS-PWM boost operation of the proposed converter can be achieved by using the boost inductor $L_f$, main switch $Q_3$, and simple auxiliary circuit at the secondary side of isolation transformer. The secondary side circuit differ from a conventional PWM boost converter by introduction a simple auxiliary circuit. The auxiliary circuit is actived only during a short switching transition time to create the ZVS condition for the main switch as that of the ZVT-PWM boost converter. With a single stage, it is possible to achieve a sinusoidal line current at unity power factor as well as the isolated 48V DC output. Comparing to the two stage schemes, overall effiency of the proposed converter is highly improved due to the effective ZVS of all devices as well as single stage power conversion. Thus, it can be operated at high switching frequency allowing use of small size input filter. Minimum voltage and current stress make it high power application possible.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.5
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• pp.422-430
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• 2014

This study proposes a small-signal model and control design for a two-stage DC-DC-AC converter to investigate its dynamic characteristics in relation to battery energy storage system. When the circuit analysis of the two-stage DC-DC-AC converter is attempted simultaneously, the mathematical procedure of deriving the dynamic equation is complex and difficult. The main idea of modeling the two-stage DC-DC-AC converter states that this topology is separated into a bidirectional DC-DC converter and a single-phase inverter with an equivalent current source corresponding to that of the inverter or converter. The dynamic equations for the separated converter and inverter are then derived using the state-space averaging technique. The procedures of building the small-signal model of the two-stage DC-DC-AC converter are described in detail. Based on the derived small-signal model, the individual controllers are designed through a frequency-domain analysis. The simulation and experimental results verify the validity of the proposed modeling approach and controller design.

• Journal of Power Electronics
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• v.12 no.5
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• pp.699-707
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• 2012

This paper proposes a single-stage half-bridge electronic ballast with a high power factor using only a single coupled inductor. Compared to conventional high power factor electronic ballasts, the proposed ballast is a simpler circuit with a low cost and a high reliability. The proposed ballast is made up of a power-factor-correction (PFC) circuit and a self-oscillating class-D inverter. The PFC and inverter stages of the proposed ballast are simplified by sharing only a single coupled inductor and two common switches. The proposed PFC circuit can achieve a high power factor and low voltage stresses of the switches. A saturable transformer in the self-oscillating class-D inverter determines the switching frequency of the ballast. Experimental results obtained on a 30W fluorescent lamp are discussed.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1069-1070
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• 2008

This paper presents a high efficient two-stage interleaved synchronous buck CMOS DC-DC converter. The proposed circuit has a fixed duty cycle as 0.5 by an added buck converter. And it causes the best ripple cancelation of the output current ripple. The proposed circuit was simulated by HSPICE with a standard CMOS $0.35{\mu}m$ process parameter.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.2
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• pp.100-105
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• 2006

In this paper, a low noise amplifier(LNA) in a receiver of a low noise block down converter (LNB) for direct broadcasting service(DBS) is implemented using GaAs HEMT. The LNA is designed for the bandwidth of 11.7 GHz-12.2 GHz. The two-stage LNA consists of a input matching circuit, a output matching circuit, DC-blocks and RF-chokes. Experimental results of the LNA show the noise figure less than 1.4 dB, the gain greater than 23 dB and the flatness of 1 dB in the bandwidth of 11.7 to 12.2 GHz.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.969-972
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• 2000

This paper proposes 1.5V-3GHz CMOS PLL with a new delay cell for operating in high frequency and multi chained two stage VCO to improve phase noise performance. The proposed multi-chained architecture is able to reduce a timing jitter or a transition spacing and the newly VCO is operating in high frequency. The PFD circuit designed to prevent fluctuation of charge pump circuit under the locking condition. Simulation results show that the tuning range of proposed VCO is wide at 1.8GHz-3.2Ghz and power dissipation is 0.6mW.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1374-1379
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• 2003

In this paper, twoㆍstage low noise amplifier(LNA) for 24㎓ is designed and fabricated using NE450284C HJ-FET of NEC CO. In order to get noise figure and input VSWR to be wanted it is considered input VSWR and noise figure simultaneously in matching-circuit designing. The fabricated two-stage low noise mph u has the gai of 16.6㏈, input VSWR of 1.6, and output VSWR under 1.5.