• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.8
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• pp.582-586
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• 2013

In this paper, a simple macro model of n-channel MOSFET with dual workfunction gate (DWFG) structure is proposed. The DWFG MOSFET has higher transconductance and lower drain conductance than conventional MOSFET. Thus analog circuit design using the DWFG MOSFET can improve circuit characteristics. Currently, device models of the DWFG MOSFET are insufficient, so simple series connected two MOSFET model is proposed. In addition, a two stage operational amplifier using the proposed DWFG MOSFET macro model is designed to verify the model.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.47-55
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• 1996

An optical transmitter, which is a key component of the optical transmission system, converts the electrical signal to optical signal and consists of a high-speed current-pulse driver for laser diode and low-speed feedback loops that stabilize optical power against aging, power supply voltage fluctuations, and ambient temperature changes. In this paper, the power-stabilizing part, which forms the bulk of the optical transmitter circuitry was designed in integrted circuits. Operational amplifiers and reference voltage generation circuits, which were identified as key building blocks for the power-stabilizing feedback loops, were designed and were subsequently verified through HSPICE simulations. The designed operational amplifier consists of a two-stage folded cascode amplifier and class AB output stage, whereas the reference voltage is obtained by bandgap reference circuits. Finally the power-stabilizing circuitry was laid out based on 3\mu$m CMOS design rules for fabrication.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.787-794
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• 1999

This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• Journal of Power Electronics
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• v.12 no.2
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• pp.258-267
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• 2012

An interleaved single-stage AC/DC converter with a boost converter and an asymmetrical half-bridge topology is presented to achieve power factor correction, zero voltage switching (ZVS) and load voltage regulation. Asymmetric pulse-width modulation (PWM) is adopted to achieve ZVS turn-on for all of the switches and to increase circuit efficiency. Two ZVS half-bridge converters with interleaved PWM are connected in parallel to reduce the ripple current at input and output sides, to control the output voltage at a desired value and to achieve load current sharing. A center-tapped rectifier is adopted at the secondary side of the transformers to achieve full-wave rectification. The boost converter is operated in discontinuous conduction mode (DCM) to automatically draw a sinusoidal line current from an AC source with a high power factor and a low current distortion. Finally, a 240W converter with the proposed topology has been implemented to verify the performance and feasibility of the proposed converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.1
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• pp.52-59
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• 2010

The conventional CCFL (Cold Cathode Fluorescent Lamp) inverter used in the backlight unit for LCD-TV, composed of the three power stage, can degrade the whole power conversion efficiency. In this paper, a novel scheme to drive the CCFL, composed only of the two power stage without using a dc/dc power stage, is proposed to enhance the whole power conversion efficiency. By adopting the proposed "4-in-1 Transformer", the current balance and the simultaneous ignition among the four CCFL lamp are assured with the one inverter circuit. The proposed scheme features the simple circuit structure, which can save the volume and the cost in the LCD backlight unit. Design considerations are discussed and design procedures are derived. Experimental results of the proposed scheme for 40" LCD-TV are presented to confirm the theoretical analysis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.328-333
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• 2006

In this paper, we developed a pressure measurement apparatus with the parallel structure to improve the measurement efficiency of pressure sensors by reducing the measurement time of pressure. The developed system has two parallel positions for loading Silicon pressure sensor and has a dual valve structure. The semiconductor pressure sensors prepared by Copal Electronics were used to confirm the performance of the developed measurement system. Two stage differential amplifier circuit was employed to amplify the weak output signal and the amplified output signal was improved utilizing a low-pass filter. New apparatus shows the measurement time of pressure two times shorter than that of conventional one with the serial structure, while both structures show the similar linear output versus pressure characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.597-605
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• 2015

Negative impedance converter(NIC)-based non-Foster impedance matching is proposed for an electrically small antenna. The antenna considered in this work is a resistively loaded vee dipole(RVD) antenna, which has considerable reflection at the feed point because of its large negative input reactance. The non-Foster matching circuit built near the feed point consists of two-stage NIC circuit and a capacitor connected between the stages. The NIC is realized by using operational amplifiers(op-amps) and resistors. The circuit is designed by considering of the input impedance according to the finite open-loop gain of the practical NICs. The stability test of the impedance-matched RVD antenna is performed. The non- Foster matching circuit is implemented with the RVD antenna. The measured impedance demonstrates that the proposed non-Foster matching circuit effectively reduces the input reactance of the RVD antenna.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1015-1026
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• 2018

A family of dual-DC-input (DI) dual-buck inverters (DBIs) is proposed by employing a DI switching cell as the input of traditional DBIs. Three power ports, i.e. a low voltage DC input port, a high voltage DC input port and an AC output port, are provided by the proposed DI-DBIs. A low voltage DC source, whose voltage is lower than the peak amplitude of the AC side voltage, can be directly connected to the DI-DBI. This supplies power to the AC side in single-stage power conversion. When compared with traditional DBI-based two-stage DC/AC power systems, the conversion stages are reduced, and the power rating and power losses of the front-end Boost converter of the DI-DBI are reduced. In addition, five voltage-levels are generated with the help of the two DC input ports, which is a benefit in terms of reducing the voltage stresses and switching losses of switches. The topology derivation method, operation principles, modulation strategy and characteristics of the proposed inverter are analyzed in-depth. Experimental results are provided to verify the effectiveness and feasibility of the proposed DI-DBIs.