• Journal of Power Electronics
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• v.14 no.5
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• pp.937-945
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• 2014

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.538-548
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• 2014

This study provides a robust control of a grid-connected three-phase two-level photo voltaic inverter. The introduced control method uses the cascade control strategy to regulate AC-side current and DC-link voltage. A robust controller with integration action is used for the inner-loop AC-side current control, which maximizes the convergence rate using a linear matrix inequality-based optimization design method and eliminates the offset error. The robust controller design method considers the parameter uncertainty set to accommodate parameter mismatch and un-modeled components in the inverter model. An outer-loop proportional-integral controller is used to regulate DC-link voltage with linearization of DC/AC relation. The proposed control strategy is applied to a grid-connected 100 kW photo voltaic inverter.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.23-26
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• 2003

This paper presents a novel hybrid type multilevel inverter in order to improve the waveshape of output voltage. The proposed multilevel inverter is consist of two full-bridge modules for level creation and one full-bridge module for PWM operation. The generated levels are total 11-level: 9-level by the level inverter and 2-level by the PWM inverter. The operational principles and analysis are explained and validity of the proposed system is verified through the experimental results using a prototype.

• Journal of Power Electronics
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• v.13 no.2
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• pp.223-231
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• 2013

A modular three-phase multilevel inverter especially suitable for electrical drive applications has been previously presented. This topology is based on series connection of power cells in which each cell comprised of two inverter legs in series. In this paper, in order to generate the maximum number of voltage levels with reduced number of switches, three algorithms are proposed for determination of the magnitudes of dc voltage sources. In addition, a new hybrid multilevel inverter is proposed that is composed of series connection of the previously presented multilevel inverter and some H-bridges. The proposed topology has been compared with some other presented multilevel inverters. The performance of the proposed multilevel inverter has been verified by simulation and experimental results of a single-phase 39-level multilevel inverter.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.1
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• pp.22-32
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• 2008

This paper proposes a linearization technique for the 3-level NPC type inverter, which increases the linear control range of Inverter up to the one-pulse inverter. The overmodulation range is divided into two modes depending on the Modulation Index, MI. In overmodulation region I, the reference angles are derived from the fourier series expansion of the reference voltage corresponding to the MI. In overmodulation region II, the holding angles are also derived in the same way. Therefore, it is possible to obtain the linear control and the maximized utilization of PWM inverter output voltage.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1027-1036
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• 2018

In this paper a new generalized space vector pulse width modulation scheme is proposed based on the principle of reverse mapping to drive the switches of multilevel inverters. This projected scheme is developed based on the middle vector of the subhexagon which holds the tip of the reference vector, which plays a major role in mapping the reference vector. A new approach is offered to produce middle vector of the subhexagon which holds tip of the reference vector in the multilevel space vector plane. By using middle vector of the subhexagon, reference vector is linked towards the inner two level sub-hexagon. Then switching vectors, switching sequence and dwell times corresponding to a particular sector of a two-level inverter are determined. After that, by using the two level stage findings, the switching vectors related to exact position of the reference vector are directly generated based on principle of the reverse mapping approach and do not need to be found at n level stage. In the reverse mapping principle, the middle vector of subhexagon is added to the formerly found two level switching vectors. The proposed generalized algorithm is efficient and it can be applied to an inverter of any level. In this paper, the proposed scheme is explained for a five-level inverter and the performance is analyzed for five level and three level inverters through MATLAB. The simulation results are validated by implementing the propose scheme on a V/f controlled three-level inverter fed induction motor using dSPACE control desk.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.448-451
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• 2000

This paper proposed a snubber circuit for flying capacitor multilevel inverter and converter. The proposed snubber circuit makes use of Undeland snubber as basic snubber as basic snubber unit and has such an advantage of Undeland snubber used in the two-level inverter. Comparing conventional RCD/RLD snubber for multilevel in verter and converter the proposed snubber keeps such a good features as fewer number of components improved efficiency of system due to low loss snubber and reduction of voltage stress of main switching devices due to low overvoltage. Furthermore the proposed concept of constructing a snubber circuit for flying capacitor 3-level inverter and converter can apply to any level of them. In this paper the proposed snubber applies to three-level flying capacitor inverter and demonstrates its feature by computer simulation and experimental result.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.5
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• pp.376-380
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• 2010

This paper presents a circuit configuration of multilevel inverter to increase the number of output voltage levels by using conventional 5-level inverters connected in series. Most of all it can maximize the number of output voltage levels by employing input voltage sources, which have the power of five. When it synthesizes the same number of output voltage levels, the proposed inverter can save the number of switching devices compared with the conventional cascaded H-bridge cell inverter. So it can reduce the size, cost, power consumption of the system. We implemented computer-aided simulation and experiments for a 25-level inverter employing two 5-level inverters.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.4
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• pp.337-343
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• 2015

The multi-level inverters are highly efficient for high-power and medium-voltage AC driving applications, such as high-speed railway systems and renewable energy resources, because such inverters generate lower total harmonic distortion (THD) and electromagnetic interface (EMI). Lower switching stress occurs on switching devices compared with conventional two-level inverters. Depending on the multi-level inverter topology, the required components and number of switching devices are different, influencing the overall efficiency. Comparative studies of multi-level inverters based on loss analysis and output characteristic are necessary to apply multi-level inverters in high-power AC conversion systems. This paper proposes a theoretical loss analysis method based on piecewise linearization of characteristic curves of power semiconductor devices as well as loss analysis and output performance comparison of five-level neutral-point clamped, flying capacitor inverters, and high-level cascaded H-bridge multi-level inverters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.746-755
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• 2001

This paper proposes a snubber circuit for flying capacitor 3-level inverter and converter. The proposed snubber circuit makes use of Undeland snubber as basic snubber unit. It has such an advantage of Undeland snubber used in the two-level inverter. Compared with conventional RLD/RCD snubber for 3-level inverter and converter, the proposed snubber keeps such good features as fewer number of components, reduction of voltage stress of main switching devices due to low overvoltage, and improved efficiency of system due to low snubber loss. In this paper, the proposed snubber is applied to multilevel flying capacitor inverter and its feature is demonstrated by computer simulation and experimental result.