• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.541-546
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• 1998

This paper proposes a new snubber circuit for multilevel inverter and converter. The snubber circuit makes use of Undeland snubber as basic snubber unit and can be regraded as a generalized Undeland snubber. The proposed snubber keeps such good features as fewer number of components, improved efficiency due to low loss snubber, capability of clamping overvoltage across main switching devices, and no unbalance problem of blocking voltage. Furthermore, the proposed concept of constructing a snubber circuit for multilevel inverter and converter can apply to any kind of basic snubber unit such as Holtz nondissipative snubber, McMurray efficient snubber, Lauritzen lossless snubber, etc which have been utilized for two-level inveter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.1928-1930
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• 1998

This paper proposes a new snubber circuit for multilevel inverter and converter. The snubber circuit makes use of Undeland snubber as basic snubber unit and can be regarded as a generalized Undeland snubber. The proposed snubber keeps such good features as fewer number of components, improved efficiency due to low loss snubber, capability of clamping overvoltage across main switching devices, and no unbalance problem of blocking voltage. Furthermore, the proposed concept of constructing a snubber circuit for multilevel inverter and converter can apply to any kind of basic snubber unit such as Holtz nondissipative snubber, McMurray efficient snubber, Lauritzen lossless snubber, etc which have been utilized for two-level inverter.

• Journal of Power Electronics
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• 제1권2호
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• pp.107-116
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• 2001

Two AC-DC PWM full-bridge converters that can input current to improve input power factor while performing dc-dc conversion are investigated in this paper. Both converters are simple in that they are similar to the standard PWM full-bridge converter with a diode rectifier/LC low-pass filter input, and both can operate with a simple method of PWM control. In the paper, the operation of the converters is explained and their steady-state characteristics are discussed. The feasibility of the converters and their ability to meet EN61000-3-2 Class D Standards for electrical equipment are shown with results obtained from experimental prototypes. The performance of both converters in terms of dc bus voltage level, input power factor and efficiency is compared and discussed.

• Journal of Power Electronics
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• 제14권6호
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• pp.1093-1099
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• 2014

This paper proposes a power conversion topology involving a multi-winding transformer and converters. The fundamental idea is described with circuit diagrams, and the voltage output of the proposed topology is analyzed mathematically. The effectiveness of the topology is discussed with test results from a small-scale power conversion system. When conventional hardware consisting of two-level converters and a transformer is employed, multi-level voltage outputs can be applied to the transformer windings by the proposed method.

• 한국정보통신학회논문지
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• 제5권4호
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• pp.746-755
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• 2001

본 논문은 플라잉 커패시터 3-레벨 인버터 및 컨버터를 위한 스너버 회로를 제안하였다. 제안한 스너버회로는 Undeland 스너버를 기본 스너버로 사용하여 구성한 것으로서, 2-레벨 인버터에서 사용되어온 Undeland 스너버의 장점을 그대로 지니고 있다. 3-레벨 인버터 및 컨버터를 위해 제안한 스너버 회로와 기존의 RCD/RLD 스너버를 비교하면 1)사용소자의 수가 감소하며, 2) 낮은 과전압에 의한 스위칭 소자의 전압 스트레스가 감소하며, 3) 스너버 회로에서의 전력손실이 감소하여 전체 시스템에서의 효율이 개선된다. 본 논문에서는 제안한 스너버를 3-레벨 플라잉 커패시터 인버터에 적용하여 스너버 특성을 컴퓨터 시뮬레이션으로 분석하였으며 실험을 통해 제안한 스너버의 효용성을 입증하였다. 제안한 플라잉 커패시터 3-레벨 인버터 및 컨버터를 위한 스너버 회로를 구성하는 방법은 멀티레벨 인버터 및 컨버터에도 그대로 적용 할 수 있다.

• Journal of Power Electronics
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• 제17권3호
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• pp.641-652
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• 2017

This paper proposes a cost-effective topology to drive a three-phase open-end load based on a five-leg indirect matrix converter (IMC) and a space vector modulation (SVM) method. By sharing an inverter leg with two load terminals, the proposed topology can reduce the number of power switches when compared to topologies based on a direct matrix converter or a six-leg IMC. The new SVM method uses only the active vectors that do not produce common-mode voltage (CMV), which results in zero CMV across the load phase and significantly reduces the peak value of the CMV at the load terminal. Furthermore, the proposed drive system can increase the voltage transfer ratio up to 1.5 and provide a superior performance in terms of an output line-to-line voltage with a three-level pulse-width modulation waveform. Simulation and experimental results are given to verify the effectiveness of the proposed topology and the new SVM method.

• Journal of Power Electronics
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• 제18권5호
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• pp.1448-1457
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• 2018

Many researchers devote themselves to develop model-predictive direct power control (MPDPC) so as to accelerate the response speed of the grid-connected systems, but they are troubled its large computing amount. On the basis of MPDPC, dual MPDPC (DMPDPC) is presented in this paper. The proposed algorithm divides the conventional MPDPC into two steps. In the first step, the optimal sector is obtained, which contains the optimal switching state in three-level converters. In the second step, the optimal switching state in the selected sector is searched to trace reference active and reactive power and balance neutral point voltage. Simulation and experiment results show that the proposed algorithm not only decreases the computational amount remarkably but also improves the steady-state performance. The dynamic response of the DMPDPC is as fast as that of the MPDPC.

• Journal of Power Electronics
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• 제13권4호
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• pp.569-583
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• 2013

In this study, the simultaneous use of a multi-level converter (MLC) as a DC-motor drive and as an active battery cell balancer is investigated. MLCs allow each battery cell in a battery pack to be independently switched on and off, thereby enabling the potential non-uniform use of battery cells. By exploiting this property and the brake regeneration phases in the drive cycle, MLCs can balance both the state of charge (SoC) and temperature differences between cells, which are two known causes of battery wear, even without reciprocating the coolant flow inside the pack. The optimal control policy (OP) that considers both battery pack temperature and SoC dynamics is studied in detail based on the assumption that information on the state of each cell, the schedule of reciprocating air flow and the future driving profile are perfectly known. Results show that OP provides significant reductions in temperature and in SoC deviations compared with the uniform use of all cells even with uni-directional coolant flow. Thus, reciprocating coolant flow is a redundant function for a MLC-based cell balancer. A specific contribution of this paper is the derivation of a state-space electro-thermal model of a battery submodule for both uni-directional and reciprocating coolant flows under the switching action of MLC, resulting in OP being derived by the solution of a convex optimization problem.

• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.263-269
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• 2018

In this study, a selective inverter operation between a 2-level voltage source converter (VSC) and a 3-level T-type VSC (3LT VSC) is proposed to improve the efficiency of a 3LT VSC. The 3LT VSC topology, except for its neutral-point switches, has similar operations as that of the 2-level VSC. If an operation mode is changed according to efficiency, the efficiency can be improved because efficiencies of each methods are depending on current and MI (Modulation Index). The proposed method calculates the power losses of the two topologies and operates as the having lower losses. To calculate the losses, the switching and conduction losses based on the operation mode of each topology were analyzed. The controller determined the operation mode of the 2- or 3-level VSC based on the power loss calculated during every cycle. The validity of the proposed control scheme was investigated through simulation and experiments. The waveform and average efficiency of each method were compared.

• Journal of Power Electronics
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• 제19권1호
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• pp.79-88
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• 2019

The neutral-point (NP) voltage of three-phase three-level NP-clamped converters is needed for balance. To maintain NP potential and suppress ripple, a novel NP voltage balancing strategy is proposed in this work. The mechanism of NP voltage variation is studied first. Then, the relationship between the disassembly of zero level (O level) and NP current is studied comprehensively. On these bases, two methods for selecting one of three output phases for the disassembly of its O level are presented. Finally, simulation and experimental results verify the validity and practicability of the proposed algorithms.