• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2007년도 춘계학술대회 논문집
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• pp.417-420
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• 2007

Micro parts are usually used of producing by micro-electro-mechanical systems(MEMS). In this paper, we present some fundamental results concerning on the MEMS, extrusion condition on the micro forming characteristics and new micro forward extrusion machine has been developed. In the first step, we manufactured micro dies in two kinds of sections. One is a circle section, another is a cross section. The process for fabricating micro dies combines a deep UV-lithography, anisotropic etching techniques and metal electroplating with bulk silicon based on Ni with a thickness of $50{\mu}m$. The outer diameter of Ni-micro dies is 3mm and the diameter of extrusion section is $270{\mu}m$ for a cross section, $500{\mu}m$ for a circle section. The low linear density polyethylene(LLEPD) in the shape of a pellet has been used of micro extrusion. The billet was placed in a container manufactured by electric discharge machining and extruded through the micro die by a piezoelectric actuator. The micro extrusion has succeeded in a forming such micro parts as micro bars, micro cross shafts.

• 한국측량학회지
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• 제28권1호
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• pp.125-132
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• 2010

최근 다양한 센서의 개발에 따라 동일한 지역에 대한 다양한 데이터들의 취득이 가능하게 되었다. 이러한 다차원 데이터를 이용하여 도시모델, 변화 탐지 등과 같은 다양한 활용분야에 적용하기 위해서 각 데이터들 간의 정합과정이 필수적이다. 본 연구에서는 기 구축된 건물모델을 참조모델로 사용하여 디지털 영상을 자동으로 정합하는 방법을 제시하였다. 두 데이터의 정합을 위해 기 구축 건물모델에서 최적정합건물을 추출 하였으며, 이를 영상에서 추출된 직선정합요소와 비교하여 최적정합건물과 상응하는 점 좌표 쌍을 추출하였다. 또한 추출된 점 좌표 쌍을 이용하여 영상데이터의 외부표정요소를 재계산함으로써 두 데이터간의 정합을 수행하였다. 실험결과는 제안된 방법이 두 데이터의 정합을 효율적으로 수행하는 것을 보여준다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• 대한두경부종양학회지
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• 제33권2호
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• pp.1-8
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• 2017

Cancer is the disease of aging and Korea is one of the fastest aging country in the world. Older patients have decreased organ function and stress tolerance, therefore are at high risk of functional decline and developing complication from cancer and cancer treatment. Before beginning cancer treatment, it is important to assess patients' life expectancy, whether the patient is likely to die of cancer or of other comorbidity, and also the risks with cancer treatment. In order to estimate patient's physiologic age, it is recommended to perform geriatric assessment and implement appropriate geriatric intervention together with meticulous supportive care, when planning cancer treatment for older patients. In a resource limited country such as Korea, two step approach of applying screening tool followed by geriatric assessment can be more efficient. Geriatric assessment is used to predict toxicity from cancer treatment such as surgery, radiotherapy, and chemotherapy, predict survival, and also to aid treatment decision. Number of randomized trials are ongoing to compare usual care versus oncogeriatric care, and with these results we expect to improve outcome of older patients with cancer.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 춘계학술대회 논문집
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• pp.819-823
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• 1996

In the large steel ingosts, void defects exhibiting microvoid shapes are inevitably formed in the V-segregation zone of the ingots during solidification. In the hot open-die forging process, material properties are improved by eliminating internal porosity. The void size is practically very small as compared with the huge large ingot. Thus, for deformation analysis of a large ingot, a massive number of elements are needed in order to describe a void surface and to uniform mesh sturcture. In the present work the Global/Local scheme has been introduced in order to reduce the computational time and to easily generate the mesh system as a void module of local mesh for obtaining the accurate solution around a void. The procedure of the global- local method consists of two steps. In the first step global analysis is carried out which seeks a reasonably good solution with a cpurse mesh system without describing a void. Then, a local analysis is performed locally with a fine mesh system under the size-criterion of a local region. The computational time has been greatly reduced. Though the work it has been shown that large ingot forging incorporation small voids can be effectively analyzed by using the proposed Global/Local scheme.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2002년도 춘계학술대회 논문집
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• pp.29-32
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• 2002

The mechanical joining process of a sheet metal pair has been developed in order to replace the resistance spot welding process in case that joining of mechanically unweldable materials and coated sheet metals with different thickness are needed. Form-joining or clinching, a kind of mechanical joining process, is defined as joining process of a sheet metal pair by geometric constraint imposed by plastic deformation of workpieces without any additive part. It has been reported that the joining strength by commercial form-joining apparatus is 50∼70 percent of that by resistance spot welding. Therefore, a two-step form-joining process with a secondary punch is proposed. The device is designed to improve the joining strength by increasing the geometric constraint of the deformed shape by combining a primary punch, a secondary punch and a female die. In order to verify the improved joining strength by the designed process, the tensile-shear strength, the peel-tension strength and the asymmetric peel-tension strength are compared with those by the TOX process and resistance spot welding.

• 마이크로전자및패키징학회지
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• 제19권2호
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Advanced Composite Materials
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• 제17권1호
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• pp.1-23
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• 2008

Robotized filament winding technology involves a robot that winds a roving impregnated by resin on a die along the directions of stresses to which the work-piece is submitted in applications. The robot moves a deposition head along a winding trajectory in order to deposit roving. The trajectory planning is a very critical aspect of robotized filament winding technology, since it is responsible for both the tension constancy and the winding time. The present work shows two original rules to plan the winding trajectory of structural parts, whose shape is obtained by sweeping a full section around a 3D curve that must be closed and not crossing in order to assure a continuous winding. The first rule plans the winding trajectory by approximating the part 3D shape with straight lines; it is called the discretized rule. The second rule defines the winding trajectory simply by offsetting a 3D curve that reproduces the part 3D shape, of a defined distance; it is called the offset rule. The two rules have been compared in terms of roving tension and winding time. The present work shows how the offset rule enables achievement of both the required aims: to manufacture parts of high structural performances by keeping the tension on the roving near to the nominal value and to markedly decrease the winding time. This is the first step towards the optimization of the robotized filament winding technology.

• 대한전자공학회논문지SD
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• 제47권5호
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• pp.87-93
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• 2010

본 논문에서는 디지털 위상동기루프에서 사용하는 고해상도와 넓은 입력 범위를 가지는 2 단계 시간-디지털 변환기(TDC)구조를 제안한다. 디지털 위상동기루프에서 디지털 오실레이터의 출력 주파수와 기준 주파수와의 위상 차이를 비교하는데 사용하는 TDC는 고해상도로 구현되어야 위상고정루프의 잡음 특성을 좋게 한다. 기존의 TDC의 구조는 인버터로 구성된 지연 라인으로 이루어져 있어 그 해상도는 지연 라인을 구성하는 인버터의 지연 시간에 의해 결정되며, 이는 트랜지스터의 크기에 의해 결정된다. 따라서 특정 공정상에서 TDC의 해상도는 어느 값 이상으로 높일 수 없는 문제점이 있다. 본 논문에서는 인버터보다 작은 값의 지연 시간을 구현하기 위해 위상-인터폴레이션 기법을 사용하였으며, 시간 증폭기를 사용하여 작은 지연 시간을 큰 값으로 증폭하여 다시 TDC에 입력하는 2 단계로 구성하여 고해상도의 TDC를 설계하였다. 시간 증폭기의 이득에 영향을 주는 두 입력의 시간 차이를 작은 값으로 구현하기 위해 지연 시간이 다른 두 인버터의 차이를 이용하여 매우 작은 값의 시간 차이를 구현하여 시간증폭기의 성능을 높였다. 제안하는 TDC는 $0.13{\mu}m$ CMOS 공정으로 설계 되었으며 전체 면적은 $800{\mu}m{\times}850{\mu}m$이다. 1.2 V의 공급전압에서 12 mA의 전류를 사용하며 0.357 ps의 해상도와 200 ps의 입력 범위를 가진다.