• Title/Summary/Keyword: Turbo decoding

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A Low-Complexity Turbo coded BICM-ID System (Turbo coded BICM-ID의 복잡도 개선 기법)

  • Kang, Donghoon;Lee, Yongwook;Oh, Wangrok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.21-27
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    • 2013
  • In this paper, we propose a low-complexity Turbo coded BICM-ID (bit-interleaved coded modulation with iterative decoding) system. A Turbo code is a powerful error correcting code with a BER (bit error rate) performance very close to the Shannon limit. In order to increase spectral efficiency of the Turbo code, a coded modulation combining Turbo code with high order modulation is used. The BER performance of Turbo-BICM can be improved by Turbo-BICM-ID using iterative demodulation and decoding algorithm. However, compared with Turbo-BICM, the decoding complexity of Turbo-BICM-ID is increased by exchanging information between decoder and demodulator. To reduce the decoding complexity of Turbo-BICM-ID, we propose a low-complexity Turbo-BICM-ID system. When compared with conventional Turbo-BICM-ID, the proposed scheme not only show similar BER performance but also reduce the decoding complexity.

High Throughput Turbo Decoding Scheme (높은 처리율을 갖는 고속 터보 복호 기법)

  • Choi, Jae-Sung;Shin, Joon-Young;Lee, Jeong-Woo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.7
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    • pp.9-16
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    • 2011
  • In this paper, various kinds of high throughput turbo decoding schemes are introduced, and a new turbo decoding scheme using the advantages of each scheme is proposed. The proposed scheme uses the decoding structure of double flow scheme, sliding window scheme and shuffled turbo decoding scheme. Simulation results show that the proposed scheme offers a BER performance equivalent to those of existing turbo decoding schemes with less clock cycles. We also show that the required memory can be reduced by choosing proper size of sliding window. Consequently, we can design a high throughput turbo decoder requiring low power and low area.

An FPGA Design of High-Speed Turbo Decoder

  • Jung Ji-Won;Jung Jin-Hee;Choi Duk-Gun;Lee In-Ki
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.6C
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    • pp.450-456
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    • 2005
  • In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

A Simple Efficient Stopping Criterion for Turbo Decoder

  • Kim, Young-Sup;Ra, Sung-Woong
    • ETRI Journal
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    • v.28 no.6
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    • pp.790-792
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    • 2006
  • The performance of a turbo decoder depends strongly on the number of iterations in its decoding process. It is necessary to stop the decoding process at an appropriate moment to alleviate the serious burden, in terms of both the computational speed and latency, part of which is associated with too many iterations. In this letter, we introduce a criterion for finding the opportune moment to stop the decoding process, called a hard decision aided criterion based on bit interleaved parity, which is known to have much simpler hardware logic, compared with other schemes, and does not lead to any significant performance degradation.

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A New Decoding Method of Turbo Code (터보코드의 복호화 기법)

  • Park Sung-Joon
    • Journal of the Korea Society for Simulation
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    • v.14 no.4
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    • pp.87-93
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    • 2005
  • In this paper we propose a new iterative decoding method of turbo code which computes the log-likelihood ratios at each MAP (maximum a posteriori) decoder in parallel in each iteration step and combines them with proper weights to produce better decisions. Our results indicate that the proposed decoding method is particularly useful for systems with limited number of iterations and low code rates.

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Effective Iterative Control Method to Reduce the Decoding Delay for Turbo TCM Decoder (터보 TCM 디코더의 복호 지연을 감소시키기 위한 효율적인 반복복호 제어기법)

  • 김순영;김정수;장진수;이문호
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.8
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    • pp.816-822
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    • 2003
  • In this paper, we propose an efficient iteration control method with low complexity for Turbo TCM(Turbo Trellis Coded Modulation) decoding which will be used fur power-limited environment. As the decoding approaches the performance limit of a given turbo code, any further iteration results in very little improvement. Therefore, it is important to devise an efficient criterion to stop the iteration process and prevent unnecessary computations and decoding delay. This paper presents an efficient algorithm for turbo TCM decoding that can greatly reduce the delay and iteration number. The proposed method use adaptive iteration number according to the criterion using the extrinsic information variance parameter in turbo TCM decoding process. The simulation results show that the proposed technique effectively can reduce the decoding delay and computation with very little performance degradation.

An FPGA Implementation of High-Speed Adaptive Turbo Decoder

  • Kim, Min-Huyk;Jung, Ji-Won;Bae, Jong-Tae;Choi, Seok-Soon;Lee, In-Ki
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.4C
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    • pp.379-388
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    • 2007
  • In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

Performance Analysis of Turbo Product Code Using Parallel Structure (병렬 구조를 이용한 Turbo Product Code 성능 분석)

  • 이태길;정지원
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.2C
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    • pp.181-186
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    • 2004
  • Recently, there has been intensive focus on Turbo Product Codes(TPCs) which have low decoding complexity and achieve near-optimum performances at high code-rate. This paper present a parallel algorithm of turbo product codes enable simultaneous decoding of row and column. The row and column decoders operate in parallel and update each other after row and column has been decoded. simulation results show that the performance of proposed parallel turbo code is almost the same as that conventional scheme for several turbo product codes.

Design and Architecture of Low-Latency High-Speed Turbo Decoders

  • Jung, Ji-Won;Lee, In-Ki;Choi, Duk-Gun;Jeong, Jin-Hee;Kim, Ki-Man;Choi, Eun-A;Oh, Deock-Gil
    • ETRI Journal
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    • v.27 no.5
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    • pp.525-532
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    • 2005
  • In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.

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A turbo code with reduced decoding delay (감소된 복호지연을 갖는 Turbo Code)

  • 김준범;문태현;임승주;주판유;홍대식;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.7
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    • pp.1427-1436
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    • 1997
  • Turbo codes, decoded through an iterative decoding algorithm, habe recently been shown to yidel remarkable coding gains close to theoretical limits in the Gaussian channel environment. This thesis presents the performance of Turbo code through the computer simulation. The performance of modified Turbo code is compared to that of the conventional Turbo codes. The modified Turbo code reduces the time delay in decoding with minimal effect to the performance for voice transmission sytems. To achieve the same performance, random interleaver the size of which is no less than the square root of the original one should be used. Also, the modified Turbo code is applied to MC-CDMA system, and its performance is analyzed under the Rayleigh Fading channel environment. In Rayleigh fading channel environment, due to the amplitude distortion caused by fading, the interleaver of the size twice no less than that in the Gaussian channel enironment was required. In overall, the modified Turbo code maintained the performance of the conventional Turbo code while the time delay in transmission and decoding was reduced at the rate of multiples of two times the squared root of the interleaver size.

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