• Journal of Astronomy and Space Sciences
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• 제21권4호
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• pp.481-492
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• 2004

Nb/Al Superconducting Tunnel Junction(STJ) 소자를 제작하여 I-V 특성곡선을 측정하고 제작된 STJ 소자의 초전도체 특성 및 성능 파라미터 값들을 구하였다. 크기가 각각 20, 40, 60, 그리고 $80{\mu}m$인 4종류의 STJ소자를 제작하였으며 각 소자는 총 5층의 Nb/A1/AlOx/Al/Nb 다결정(polycrystalline) 박막으로 구성된 SIS(Superconductor Insulate. Superconductor) 방식의 조셉슨 접합 구조를 갖는다. 이 연구에서 제작한 STJ 소자는 $Tanner^{TM}$ L-Edit 8.3 프로그램으로 설계하였으며 한국표준과학연구원의 SQUID 제조실험실에서 제작하였다. 5층의 STJ 박막은 DC magnetron sputtering, reactive ion etching, CVD(Chemical Vapor Deposition) 장비를 이용해 생성되었다. 제작된 STJ 소자는 액체헬륨으로 냉각(4K)시킨 후 I-V 특성곡선을 측정하여 초전도 특성을 확인하였고, STJ 소자의 성능을 결정하는 파라미터인 energy gap, normal resistance, normal resistivity, dynamic resistance, dynamic resistivity, 그리고 quality factor를 계산하였다. Nb/Al STJ 소자의 FWHM 에너지 분해능 계산 결과, 순수 Nb STJ 소자보다 $11\%$ 우수한 에너지 분해능 특성을 확인하였다.

• Progress in Superconductivity
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• 제12권2호
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• pp.114-117
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• 2011

We report our efforts on the development of Nb-based non-hysteretic Josephson junction fabrication process for quantu device applications. By adopting and modifying the existing Nb-aluminum oxide tunnel junction process, we develop a process for non-hysteretic Josephson junction circuits using metal-silicide as metallic barrier material. We use sputter deposition of Nb and $MoSi_2$, PECVD deposition of silicon oxide as insulator material, and ICP-RIE for metal and oxide etch. The advantage of the metal-silicide barrier in the Nb junction process is that it can be etched in $SF_6$ RIE together with Nb electrode. In order to define a junction area precisely and uniformly, end-point detection for the RIE process is critical. In this paper, we employed thin Al layer for the etch stop, and optimized the etch condition. We have successfully demonstrated that the etch stop properties of the inserted Al layer give a uniform etch profile and a precise thickness control of the base electrode in Nb trilayer junctions.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.381-382
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• 2018

무접합 나노선 터널 전계 효과 트렌지스터(junctionless nanowire tunnel field-effect transistor; JLNW-TFET)에서 소스(p+), 채널(i), 드레인(n) 물질으로 실리콘 및 게르마늄을 사용하여 이 구조에 대한 문턱전압 이하 기울기(subthreshold swings; SS)와 구동전류를 관찰했다. 소스-채널을 게르마늄-실리콘일 때 실리콘-실리콘, 실리콘-게르마늄, 게르마늄-게르마늄 구조보다 구동전류가 최대 1000배 증가하였고, 실리콘-실리콘 구조가 다른 구조에 비해 최소 SS가 최대 5배 이상 감소하였다.

• Journal of Magnetics
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• 제14권1호
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• pp.11-14
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• 2009

We investigated the I-V curves and differential tunneling conductance of two, CoFeB/MgO/CoFeB-based, magnetic tunnel junctions (MTJs): one with a low tunneling magnetoresistance (TMR; 22%) and the other with a high TMR (352%). This huge TMR difference was achieved by different MgO sputter conditions rather than by different annealing or deposition temperature. In addition to the TMR difference, the junction resistances were much higher in the low-TMR MTJ than in the high-TMR MTJ. The low-TMR MTJ showed a clear parabolic behavior in the dI/dV-V curve. This high resistance and parabolic behavior were well explained by the Simmons' simple barrier model. However, the tunneling properties of the high-TMR MTJ could not be explained by this model. The characteristic tunneling properties of the high-TMR MTJ were a relatively low junction resistance, a linear relation in the I-V curve, and conduction dips in the differential tunneling conductance. We explained these features by applying the coherent tunneling model.

• Journal of Magnetics
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• 제7권3호
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• pp.101-105
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• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.123-126
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• 2002

Samples of Nb/Al-Al$O_{x}$/Nb tunnel junction with the size of 50$\mu$m $\times$ 50$\mu$m were fabricated by employing self-aligning and reactive ion etching technique. In the samples with high-quality, $V_{m}$ value (the product of the critical current and subgap resistance measured at 2 mV) was 34 mV at the critical current density $J_{c}$ = 500 A/$cm^{2}$ and $V_{g}$ value (the gap voltage) was 2.8 mV. In the higher $J_{c}$, voltage fluctuation in the current rising at the gap voltage was observed. The $V_{m}$ and $J_{c}$ value were 8 mV and 900 A/$cm^{2}$, respectively.

• 반도체디스플레이기술학회지
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• 제5권1호
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• pp.17-20
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• 2006

This paper presents of a new type of memory cell that could potentially replace both DRAM and flash memory. The proposed device cell operates by sensing the state of about 1,000 electrons trapped between unique insulating barriers in the channel region of the upper transistor. These electrons are controlled by a side gate on the transistor, and their state in turn controls the gate of the larger transistor, providing signal gain within the memory cell. It becomes faster and more reliable memory with lower operation voltage. Moreover, the use of a multiple tunnel junction (MTJ) fur the vertical transistor can significantly improve the data retention and operation speed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1402-1404
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• 2001

Josephson junction arrays of the type $Nb/Al-Al_2O_3/Nb$ were prepared by DC magnetron sputtering. The tunnel barrier was formed by in-situ thermal oxidation. Individual junctions were defined using selective niobium etching process(SNEP). The characteristic curves of Josephson junction arrays fabricated with and without cooling the substrate were represented. The junctions deposited without cooling showed poor characteristics(high leakage current, low gap voltage), and a high quality Josephson junction array of 2,000 junctions with high hysteresis was obtained with cooling and when operated at 74.6 GHz, it generated stable quantized voltage steps up to 2.2 V.

• E2M - 전기 전자와 첨단 소재
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• 제11권11호
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• pp.37-45
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• 1998

In this paper, present status of super high-efficiency tandem solar cells has been reviewed and key issues for realizing super high-efficiency have also been discussed. In addition, the terretrial R&D activities of tandem cells, in the New Sunshine Program of MITI(Ministry of International Trade and Industry) and NEDO(New Energy and Industrial Technology Development Organization) in Japan are reviewed briefly. The mechanical stacked 3-junction cells of monolithically grown InGaP/GaAs 2-junction cells and InGaAs cells have reached the highest efficiency achieved in Japan of 33.3% at 1-sun AM1.5. This paper also reports high-efficiency InGaP/GaAs 2-junction solar cells with a world-record efficiency of 26.9% at AM0, 28$^{\circ}C$ and radiation damage recovery phenomena of the tandem cell performance due to minority-carrier injection under light illumination or forward bias, which causes defect annealing in InGaP top cells. Future prospects for realizing super-high efficiency and low-cost tandem solar cells are also described.