• Journal of the Semiconductor & Display Technology
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• v.8 no.2
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• pp.59-62
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• 2009

In order to check the validation of LC simulation, 0.7 inch LCOS panel in full-HD resolution was fabricated and used for the electro-optical measurement. Compared the measured data with the calculated data, the averaged difference was 1.72% under 0 ~ +6 V bias on pixel electrode. To improve the optical characteristics of full-HD LCOS panel, the planar structure and trench structures (0.1 um, 0.2 um and 0.3 um-in-depth) between adjacent pixels were investigated with LC simulation. The planar structure showed the higher reflectance and faster reflectance-voltage response time than the trench structure. The optical fill factor and contrast ratio of planar structure were also higher than those of trench structures. As compared 1 um-in-depth trench structure resembled to the real structure with the planar structure, the optical fill factor was improved by 1.15% and the contrast ratio was improved by 5.26%. In order to minimize the loss of luminance and contrast ratio, the planar structure need to be applied between adjacent pixels.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.9
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• pp.523-526
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• 2000

A dual gate trench emitter IGBT structure is proposed and studied numerically using the device simulator MEDICI. The on-state forward voltage drop latch-up current density turn-off time and breakdown voltage of the proposed structure are compared with those of the conventional DMOS-IGBT and trench gate IGBT structures. The proposed structure forms an additional channel and increases collector current level resulting in reduction of on -state forward voltage drop. In addition the trench emitter increases latch-up current density by 148% in comparison with that for the conventional DMOS-IGBT and by 83% compared with that for the trench gate IGBT without degradation in breakdown voltage when the half trench gate width(Tgw) and trench emitter depth(Ted) are fixed at $1.5\mum\; and\; 2\mum$, respectively

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.353-358
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• 2007

J-shaped superluminescent diodes (SLD) utilizing trench structure have been fabricated on the multiple quantum dots epi-structure with its ground state energy wavelength of $1.3\;{\mu}m$. It was observed that optical power was drastically increased up to 20 times in comparison with that of SLD without trench structure, The electroluminescence characteristics showed that the peak intensity of excited state was several ten times higher in the SLD with trench than without trench structure. It is explained that the optical power enhancement of J-shaped SLD with trench structure resulted from the drastic increase of peak intensity of excited state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.88-89
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• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• Korean Journal of Optics and Photonics
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• v.14 no.1
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• pp.33-37
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• 2003

A low-power $1{\times}2$ polymeric thermo-optic switch with a trench structure is proposed and fabricated. The trench structure in the optimized region slows down the heat flow from the electrodes, which contributes to the reduction of power consumption. The temperature distribution in the polymer layers has been adjusted to increase the temperature gradient between the two arms of the Y-branch. For comparison, a $1{\times}2$ polymeric thermo-optic switch with no trench structure is fabricated together on the same substrate. In the device with a trench structure, the measured crosstalk is less than -17.0 dB for TE polarization.-15.0 dB for TM polarization. The power consumption is about 66 mW, which is 25% less than that of the device with no trench structure.

• Korean Journal of Optics and Photonics
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• v.6 no.4
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• pp.373-378
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• 1995

Bending losses of bent optical waveguides are calculated by virtue of the finite difference-beam p propagation method in the cylindrical coordinate system. In order to minimize the radiating losses of bent optical waveguides, we apply the trench structure to the bent waveguides and perform the a analysis to keep track of: 1) the influence of curvature radius on the bending loss without the trench, 2) the influence of curvature radius and refractive index difference on the bending loss with the trench, 3) the influence of the trench width on the bending loss.

• Journal of IKEEE
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• v.25 no.2
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• pp.356-361
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• 2021

Super Junction structure is the proposed structure to minimize the Trade-off phenomenon of power devices. Super Junction can have On-resistance(Ron) characteristics as less as five times than conventional structure. There are process methods that Multi-Epi and Deep-Trench of Super Junction structure. The reason for this is that Deep-Trench process is known to be a relatively difficult manufacturing method because it is easy to form a P-Pillar by burying impurities on top of a silicon substrate through a Deep-Trench process. However, the structure created by the Deep-Trench process has low On-resistance and high breakdown voltage, showing better efficiency. In this paper, we suggested a novel method in the process and designed structure with Charge Balance theory.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.257-260
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• 2003

We have proposed the junction termination structure of IGBT (Insulated Gate Bipolar Transistor) by employing trench and FLR (Field Limiting Ring), which decrease the junction termination area at the same breakdown voltage. Our proposed junction termination structure, trench FLR is verified by numerical simulator MEDICI. In 600V rated device, the junction termination area is decreased 20% compared with that of the conventional FLR structure. The breakdown voltage of trench FLR with 4 trenches is 768 V, 99 % of ideal parallel-plane junction(1-D) $BV_ceo$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.912-917
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• 2006

In this paper, Trench emitter electrode IGBT structure is proposed and studied numerically using the device simulator, MEDICI. The breakdown voltage, on-state voltage drop, latch up current density and turn-off time of the proposed structure are compared with those of the conventional trench gate IGBT(TIGBT) structures. Enhancement of the breakdown voltage by 19 % is obtained in the proposed structure due to dispersion of electric field at the edge of the bottom trench gate by trench emitter electrode. In addition, the on-state voltage drop and the latch up current density are improved by 25 %, 16 % respectively. However increase of turn-off time in proposed structures are negligible.

• Journal of IKEEE
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• v.25 no.1
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• pp.15-24
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• 2021

In this paper, 1700 V EPDT (Extended P+ shielding floating gate Double Trench) MOSFET structure, which has a smaller switching time and loss than CDT (Conventional Double Trench) MOSFET, is proposed. The proposed EPDT MOSFET structure extended the P+ shielding area of the source trench in the CDT MOSFET structure and divided the gate into N+ and floating P- polysilicon gate. By comparing the two structures through Sentaurus TCAD simulation, the on-resistance was almost unchanged, but Crss (Gate-Drain Capacitance) decreased by 32.54 % and 65.5 %, when 0 V and 7 V was applied to the gate respectively. Therefore, the switching time and loss were reduced by 45 %, 32.6 % respectively, which shows that switching performance was greatly improved.