• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.19-22
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• 2003

In this paper, a new small size Lateral Trench Electrode Power MOSFET with local doping is proposed. This new structure is based on the conventional lateral power MOSFET. The entire electrodes of proposed device are placed in trench oxide. The forward blocking voltage of the proposed device is improved by 3.3 times with that of the conventional lateral power MOSFET. The forward blocking voltage of proposed device is about 500V. At the same size, a increase of the forward blocking voltage of about 3.3 times relative to the conventional lateral power MOSFET is observed by using TMA-MEDICI which is used for analyzing device characteristics. Because the electrodes of the proposed device are formed in trench oxide respectively, the electric field in the device are crowded to trench oxide. And because of the structure which has a narrow drain doping width, the punch through breakdown can be occurred in higher voltage than that of conventional lateral power MOSFET. We observed that the characteristics of the proposed device was improved by using TMA-MEDICI and that the fabrication of the proposed device is possible by using TMA-TSUPREM4.

• 전기전자학회논문지
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• 제25권2호
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• pp.350-355
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• 2021

IGBT는 MOSFET과 BJT의 구조를 동시에 포함하고 있는 전력반도체 소자이며, MOSFET의 빠른 스위칭 속도와 BJT의 고 내압, 높은 전류내량 특성을 갖고 있다. GBT는 높은 항복전압, 낮은 V_CE-SAT, 빠른 스위칭 속도, 고 신뢰성의 이상적인 파워 반도체 소자의 요구사항을 목표로 하는 소자이다. 본 논문에서는 1,200V 급 Trench Gate Field Stop IGBT의 상단 공정 파라미터인 Gate oxide thickness, Trench Gate Width, P+ Emitter width를 변화시키면서 변화하는 Eoff, V_CE-SAT을 분석하였고, 이에 따른 최적의 상단 공정 파라미터를 제시하였다. Synopsys T-CAD Simulator를 통해 항복전압 1,470V와 V_CE-SAT 2.17V, Eon 0.361mJ, Eoff 1.152mJ의 전기적 특성을 갖는 IGBT 소자를 구현하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.74-75
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• 2008

TIGBT has some merits which are lower on-state voltage drop and smaller cell pitch, but also has a defect which is relatively lower breakdown voltage in comparison with planar IGBT. This lower breakdown voltage is due to the electric field which is concentrated on beneath the vertical gate. Therefore in this paper, new trench IGBT structure is proposed to improve breakdown voltage In the new proposed structure, a narrow oxide beneath the trench gate edge where the electric field is concentrated is extended into rectangular shape to decrease the electric field. As a result, breakdown voltage is improved to 23%.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.67-70
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• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.84-85
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• 2005

Dislocations are often found at Shallow Trench Isolation (STI) process after repeated thermal cycles. The residual stress after STI process often leads defect like dislocation by post STI thermo-mechanical stress. Thermo-mechanical stress induced by STI process is difficult to remove perfectly by plastic deformation at previous thermal cycles. Embedded flash memory process is very weak in terms of post STI thermo-mechanical stress, because it requires more oxidation steps than other devices. Therefore, dislocation-free flash process should be optimized.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.74-74
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• 2009

The ArF PR mask was. developed to overcome the limit. of sub 40nm patterning technology with KrF PR. But ArF PR difficult to meet the required PR selectivity by thin PR thickness. So need to the multi-stack mask such as amorphous carbon layer (ACL). Generally capacitively coupled plasma (CCP) etcher difficult to make the high density plasma and inductively coupled plasma (ICP) type etcher is more suitable for multi stack mask etching. Hybrid Coupled Plasma source (HCPs) etcher using the 13.56MHz RF power for ICP source and 2MHz and 27.12MHz for bias power was adopted to improve the process capability and controllability of ion density and energy independently. In the study, the oxide trench which has the multi stack layer process was investigated with the HCPs etcher (iGeminus-600 model DMS Corporation). The results were analyzed by scanning electron microscope (SEM) and it was found that etching characteristic of oxide trench profile depend on the multi-stack mask.

• Transactions on Electrical and Electronic Materials
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• 제2권3호
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• pp.24-27
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• 2001

The end point of oxide chemical mechanical polishing (CMP) have determined by polishing time calculated from removal rate and target thickness of oxide. This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, it was investigated the removal properties of PETEOS blanket wafers, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the oxide removal amounts of blanket and patterned wafers. We analyzed this relationship, and the post CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafer (correlation factor: 0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formula. As the result of repeatability test, the differences of calculated polishing time and actual polishing time was about 3.48 seconds. If this time is converted into the thickness, then it is from 104 $\AA$ to 167 $\AA$. It is possible to be ignored because process margin is about 1800 $\AA$.

• 한국진공학회지
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• 제11권4호
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• pp.212-217
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• 2002

고신뢰성 트렌치 게이트 MOSFET을 제작하기 위해 트렌치 코너를 pull-back 공정과 수소 열처리 공정을 이용하여 트렌치 코너를 둥글게 만드는 기술을 개발하였고 이를 이용하여 균일한 트렌치 게이트 산화막을 성장시킬수 있었다. 그 결과 수소 열처리 하기 전에 항복전압이 29 V인 것이 수소 열처리한 후 약 36 V로 증가하여 항복 전압에서 약 25% 향상되었다. 그리고 트렌치 게이트를 이용한 MOSFET에서 트렌치 셀이 약 45,000개 일때 게이트와 소스에 10 V를 인가했을 때, 드레인 전류는 약 45.3 A를 얻었고, 게이트 전압의 10 V, 전류를 5 A를 인가한 상태에서 On-저항은 약 55 m$\Omega$ 얻었다.

• Transactions on Electrical and Electronic Materials
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• 제2권3호
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• pp.33-37
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• 2001

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improves snapback which leads to a lot of problems of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor (EST) with trench electrode has been proposed for improving snab-back effect. It is observed that the forward blocking voltage of the proposed device is 745V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• 전기전자학회논문지
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• 제20권3호
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• pp.220-225
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• 2016

본 논문은 전류 센싱 FET가 내장되어 있고 온-저항이 낮으며 고전류 구동이 가능한 트렌치 게이트 고 전력 MOSFET를 제안하고 전기적 특성을 분석하였다. 트렌치 게이트 전력 소자는 트렌치 폭 $0.6{\mu}m$, 셀 피치 $3.0{\mu}m$로 제작하였으며 내장된 전류 센싱 FET는 주 전력 MOSFET와 같은 구조이다. 트렌치 게이트 MOSFET의 집적도와 신뢰성을 향상시키기 위하여 자체 정렬 트렌치 식각 기술과 수소 어닐링 기술을 적용하였다. 또한, 문턱전압을 낮게 유지하고 게이트 산화막의 신뢰성을 증가시키기 위하여 열 산화막과 CVD 산화막을 결합한 적층 게이트 산화막 구조를 적용하였다. 실험결과 고밀도 트렌치 게이트 소자의 온-저항은 $24m{\Omega}$, 항복 전압은 100 V로 측정되었다. 측정한 전류 센싱 비율은 약 70 정도이며 게이트 전압변화에 대한 전류 센싱 변화율은 약 5.6 % 이하로 나타났다.