• Transactions of The Korea Fluid Power Systems Society
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• v.6 no.2
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• pp.14-21
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• 2009

The typical hydraulic hoisting system of the rack-bar type sluice gate is composed of a hydraulic supply unit using an uni-directional pump, a direction control valve, a hydraulic motor, a counter balance valve, and flow control valves. Here, the hydrostatic transmission is applied to the hoisting system of rack-bar type sluice gate to simplify the operation of gate such that the upward and downward direction of gate is simply controlled by the direction of pump rotation. The new hydraulic hoisting system is composed of a bi-directional pump, a hydraulic motor, two counter balance valves, two check valves, two pilot-operated check valves, two relief valves and a shuttle valve. The characteristics of a suggested system are analyzed by computer simulations.

• Transactions of The Korea Fluid Power Systems Society
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• v.7 no.4
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• pp.15-22
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• 2010

The typical hydraulic hoisting system of the rack-bar type sluice gate is composed of a hydraulic supply unit using an uni-directional pump, a direction control valve, a hydraulic motor, a counter balance valve, and flow control valves. Here, the hydrostatic transmission is applied to the hoisting system of rack-bar type sluice gate to simplify the operation of gate such that the upward and downward direction of gate is simply controlled by the direction of pump rotation. The new hydraulic hoisting system is composed of a bi-directional pump, a hydraulic motor, a counter balance valve, two check valves, two pilot-operated check valves, two relief valves and a shuttle valve. The characteristics of a suggested system are analyzed by computer simulations and experiments.

• 유공압시스템학회:학술대회논문집
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• 2010.06a
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• pp.86-92
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• 2010

The typical hydraulic hoisting system of the rack-bar type sluice gate is composed of a hydraulic supply unit using an uni-directional pump, a direction control valve, a hydraulic motor, a counter balance valve, and flow control valves. Here, the hydrostatic transmission is applied to the hoisting system of rack-bar type sluice gate to simplify the operation of gate such that the upward and downward direction of gate is simply controlled by the direction of pump rotation. The new hydraulic hoisting system is composed of a bi-directional pump, a hydraulic motor, a counter balance valve, two check valves, two pilot-operated check valves, two relief valves and a shuttle valve. The characteristics of a suggested system are analyzed by computer simulations and experiments.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.467-468
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• 2008

In this paper, a logic family, the transmission gate CMOS(TG CMOS) is proposed, which combines the transmission gate and pass transistor resulting in a different configuration from traditional full CMOS. In the simulation, basic cells comprising this logic are designed and their dynamic responses are analyzed. The simulation shows their performance is exceeding that of conventional full CMOS.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.861-863
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• 2005

LMP based congestion management method is suggested as an effective tool, because network congestion can be handled by energy price. It is now being widely used in the North American Electricity Markets. Among them, FGR(Flow-gate rights) is considered to be appropriate for our system, as power flow through the congested line is unidirectional and congestion occurs in the known place. In the CBP market, hedging through transmission right is not necessary even though location pricing system is adopted, because there are no risks in the energy price. Rut, transmission rights should be adopted in the advanced market. Key issue when implementing FGR is how to decide transmission right issuance quantify. This paper deals with a method to decide transmission right issuance quantity by using power. Transfer Distribution Factor(PTDF).

• Journal of Electrical Engineering and Technology
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• v.6 no.6
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• pp.824-828
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• 2011

Transmission line analysis of the surface a cumulation layer in injection-enhanced gate transistor (IEGT) is presented for the first time, based on per-unit-length resistance and conductance of the surface layer beneath the gate of IEGT. Lateral electric field on the accumulation layer surface, as well as the electron current injected into the accumulation layer, is governed by the well-known wave equation, and decreases as an exponential function of the lateral distance from the cathode. Unit-length resistance and conductance of the layer are expressed in terms of the device parameters and the applied gate voltage. Results obtained from the experiments are consistent with the numerical simulations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.21-25
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• 1999

In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. In the result, we get amplitude of logic voltage of 200mV, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26ns in AC characteristic output of Ring-Oscillator connected Gate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.1
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• pp.93.2-93.2
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• 2012

Point Spread Function (PSF) is one of the most important optical characteristics for describing the performance of a telescope. And a concept of subpixelization is inevitable in evaluating the undersampled PSF (Shin and Sakurai 2009). Then, the internal structure of Yohkoh SXT CCD pixel is not uniform: For the top half of pixel area, the X-ray should pass a so-called gate structure where the charges are transferred to an output amplifier. This gate structure shows energy-dependent sensitivity (Tsuneta et al. 1991). For example, for Al-K (8.34 A) X-ray emission, the transmission of the polysilicon gate is about 0.9. Also, for the peak coronal response of the SXT thin filters, around 17 angstrom (0.729 keV), the transmission of the gate is about 0.6, falling off sharply towards longer wavelengths. It should be noted that this spectrally dependent non-uniform response of each CCD pixel will certainly have a noticeable effect on the properties of the PSF at longer wavelengths. Therefore, especially for analyzing the undersampled PSF of low energy source, a careful consideration of non-uniform internal pixel structure is required in determining the shape of the PSF core. The details on the effect of gate structure will be introduced in our presentation.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.273-280
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• 2017

As massive integration technology of transistors has been developing, multi-core circuit is fabricated on a silicon chip and a clock frequency is getting faster to meet the system requirement. But increasing the clock frequency can induce some problems to violate the operation of system such as clock synchronization, so it is very import to avoid metastability events to design digital chips. In this paper, metastability windows are measured by bisection method in H-spice depending on temperature, supply voltage, and the size of transmission gate with D-FF designed with 180nm CMOS process. The simulation results show that the metastability window(: MW) is slightly increasing to temperature and supply voltage, but is quadratic to the area of a transmission gate, and the best area ration of P and Ntransitor in transmission gate is P/N=4/2 to get the least MW.