• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.473-479
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• 2011

In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO ($N_c$-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (${\mu}_{FE}$) of $N_c$-embedded-IGZO TFT was 2.37 $cm^2/Vs$ and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (${\mu}_{FE}$ of a-IGZO was 9.67 $cm^2/Vs$ and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (${\Delta}V_{TH}$) of $N_c$-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during $10^5$ s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.162-162
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• 2010

InAs 는 광전자 및 광통신 소자에 널리 이용되는 $In_xGa_{1-x}As_yP_{1-y}$ 화합물의 endpoint 로서, Heterojunction Field-Effect Transistors (HEMTs), Heterojunction Bipolar Transistor (HBT) 등에 중요하게 이용되고, 다양한 소자의 기판으로도 폭넓게 사용되는 물질이다. InAs 의 반도체 소자로의 응용을 위해서는 정확한 광 특성과 밴드갭 값들이 필수적이며, 분광타원편광분석법(ellipsometry) 을 이용한 상온 InAs 유전율 함수는 이미 정확히 알려져 있다. 그러나 상온에서는 $E_2$ 전이점 영역에서 여러 개의 밴드갭들이 중첩되어 있어, 밴드구조계산 등에 필수적인 InAs의 전이점을 정확히 정의하기 어렵다. 또한, 현재의 산업계에서 중요하게 여겨지는 실시간 모니터링을 위해서는 증착온도에서의 유전율 함수 데이터베이스가 필수적이다. 이와 같은 필요성에 의해, 22 K - 700 K 의 온도범위에서 InAs 의 유전율 함수와 밴드갭 에너지에 대한 연구를 수행하였다. InAs bulk 기판을 methanol, acetone, DI water 등으로 세척 한 뒤, 저온 cryostat 에 부착하였다. 분광타원분석법은 표면의 오염에 매우 민감하기 때문에, 저온에서의 응결 방지를 위해 고 진공도를 유지하며, 액체 헬륨으로 냉각하였다. 0.7 - 6.5 eV 에너지 영역에서 측정이 가능한 분광타원편광분석기로 측정한 결과, 온도가 증가함에 따라 열팽창과 phonon-electron 상호작용효과의 증가에 의해, 밴드갭 에너지 값의 적색 천이와 밴드갭들의 중첩을 관찰 할 수 있었다. 정확한 밴드갭 에너지 값의 분석을 위하여 2계 미분을 통한 표준 밴드갭 해석법을 적용하였으며, 22 K 의 저온에서는 $E_2$ 전이점 영역에서 중첩된 여러 개의 밴드갭들을 분리 할 수 있었다. 또한 고온에서의 연구를 통해, 실시간 분석을 위한 InAs 유전함수의 데이터베이스를 확립하였다. 본 연구의 결과는 InAs 를 기반으로 한 광전자 소자의 개발 및 적용분야와 밴드갭 엔지니어링 분야에 많은 도움이 될 것으로 예상한다.

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.33-36
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• 2009

Inorganic-organic composite thin-film-transistors (TFTs) of ZnO nanowire/Poly(3-hexylthiophene) (P3HT) were investigated by changing the nanowire densities inside the composites. Crystalline ZnO nanowires were synthesized via an aqueous solution method at a low temperature, and the nanowire densities inside the composites were controlled by changing the ultrasonifiaction time. The channel layers were prepared with composites by spin-coating at 2000 rpm, which was followed by annealing in a vacuum at $100^{\circ}C$ for 10 hours. Au/inorganic-organic composite layer/$SiO_2$ structures were fabricated and the mobility, $I_{on}/I_{off}$ ratio, and threshold voltage were then measured to analyze the electrical characteristics of the channel layer. Compared with a P3HT TFT, the electrical properties of TFT were found to be improved after increasing the nanowire density inside the composites. The mobility of the P3HT TFT was approximately $10^{-4}cm^2/V{\cdot}s$. However, the mobility of the ZnO nanowire/P3HT composite TFT was increased by two orders compared to that of the P3HT TFT. In terms of the $I_{on}/I_{off}$ ratio, the composite device showed a two-fold increase compared to that of the P3HT TFT.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.696-706
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• 2007

Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

• Journal of Industrial and Engineering Chemistry
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• v.68
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• pp.117-123
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• 2018

Recently, aqueous method has attracted lots of attention because it enables the solution-processed metal oxide thin film with high electrical properties in low temperature fabrication condition to various flexible devices. Focusing the development of aqueous route, many researchers are only focused on metal oxide materials. However, for expansive application of the aqueous-based metal oxide films, the systematic study of performance change with process variables for the development of aqueous-based metal oxide insulator film is urgently required. Here, we propose importance of process variables to achieve high electrical-performance metal oxide insulator based on the aqueous method. We found that the significant process variables including precursor solution temperature and humidity during the spincoating process strongly affect chemical, physical, and electrical properties of $AlO_x$ insulators. Through the optimization of significant variables in process, an $AlO_x$ insulator with a leakage current value approximately $10^5$ times smaller and a breakdown voltage value approximately 2-3 times greater than un-optimized $AlO_x$ was realized. Finally, by introducing the optimized $AlO_x$ insulators to solutionprocessed $InO_x$ TFTs, we successfully achieved $InO_x/AlO_x$ TFTs with remarkably high average field-effect mobility of ${\sim}52cm^2V^{-1}\;s^{-1}$ and on/off current ratio of 106 at fabrication temperature of $250^{\circ}C$.

• Journal of Radiation Industry
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• v.9 no.1
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• pp.1-7
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• 2015

The trend of x-ray image sensor has been evolved from an amorphous silicon sensor to a crystal silicon sensor. A crystal silicon X-ray sensor, meaning a X-ray CIS (CMOS image sensor), is consisted of three transistors (Trs), i.e., a Reset Transistor, a Source Follower and a Select Transistor, and a photodiode. They are highly sensitive to radiation exposure. As the frequency of exposure to radiation increases, the quality of the imaging device dramatically decreases. The most well known effects of a X-ray CIS due to the radiation damage are increments in the reset voltage and dark currents. In this study, a pixel array of a X-ray CIS was made of $20{\times}20pixels$ and this pixel array was exposed to a high radiation dose. The radiation source was Co-60 and the total radiation dose was increased from 1 to 9 kGy with a step of 1 kGy. We irradiated the small pixel array to get the increments data of the reset voltage and the dark currents. Also, we simulated the radiation effects of the pixel by MCNP (Monte Carlo N-Particle) simulation. From the comparison of actual data and simulation data, the most affected location could be determined and the cause of the increments of the reset voltage and dark current could be found.

• Journal of Industrial and Engineering Chemistry
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• v.68
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• pp.399-405
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• 2018

We report the fabrication of organic field-effect transistors (OFETs) via spray coating of electrochemically exfoliated graphene (EEG) and conducting polymer hybrid as electrodes. To reduce the roughness and sheet resistance of the EEG electrodes, subsequent coating of conducting polymer (poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS)) and acid treatment was performed. After that, active channel layer was developed by spin coating of semiconducting poly(3-hexylthiophene) on the hybrid electrodes to define the bottom gate bottom contact configuration. The OFET devices with the EEG/PEDOT:PSS hybrid electrodes showed a reasonable electrical performances (field effect mobility = $0.15cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^2$, and threshold voltage = -1.57V). Furthermore, the flexible OFET devices based on the Polydimethlsiloxane (PDMS) substrate and ion gel dielectric layer exhibited higher electrical performances (field effect mobility = $6.32cm^2V^{-1}\;s^{-1}$, on/off current ratio = $10^3$, and threshold voltage = -1.06V) and excellent electrical stability until 1000 cycles of bending test, which means that the hybrid electrode is applicable to various organic electronic devices, such as flexible OFETs, supercapacitors, organic sensors, and actuators.