• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.68-76
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• 1994

In the automatic transistor sizing with computer for optimizing delay and the chip area of CMOS digital circuits, conventionally either a mathematical method or a heuristic method has been used. In this paper, we present a new method of transistor sizing, a sort of combination of the above two methods, in which the mathematical method is used for sizing of critical paths and the heuristic method is used for desizing of non-critical paths. In order to reduce the overall problem dimension, a basic block called an extended stage is introduced which includes a basic stage, parallel transistors and complementary part. Optimization for multiple critical paths is formulated as a problem of area minimization subject to delay constraints and is solved by the augmented Lagrange multiplier method. The transistor sizes along non-critical paths are decreased successively without affecting the critical path delay times. The proposed scheme was successfully applied to several test circuits.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.403-405
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.106-109
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• 2004

A high-density 3-transistor cell one-time programmable (OTP) ROM array using standard CMOS Gate-Oxide antifuse (AF) is proposed, fabricated, and characterized with $0.18{\mu}m$ CMOS process. The proposed non-volatile high-density OTP ROM is composed of an array of 3-T OTP cells with the 3-T consisting of an nMOS AF, a high voltage (HV) blocking transistor, and a cell access transistor, all compatible with standard CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.2
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• pp.7-14
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• 1979

Design considerations of I2L are discussed with particular emphasis on the upward current gain of the npn transistor, 6J Several test structures have been fabricated to measure the DC and AC characteristics of the I2L basic cell and the base current components of the npn transistor. A T flip-flop has also been designed and fabricated using the I2L technology. The upward current gain of 10 the speed -power product of the 2.6pJ/gate and the minimum propagation delay time of 36 nsec have been obtained from the test structure. The maxmum toggle frequency of the T flip -flop has been measured to be 3.5 MHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.759-763
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• 2016

We demonstrate the utilization of ion gel gate dielectrics for operating non-volatile transistor memory devices based on polymer semiconductor thin films. The gating process in typical electrolyte-gated polymer transistors occurs upon the penetration and escape of ionic components into the active channel layer, which dopes and dedopes the polymer film, respectively. Therefore, by controlling doping and dedoping processes, electrical current signals through the polymer film can be memorized and erased over a period of time, which constitutes the transistor-type memory devices. It was found that increasing the thickness of polymer films can enhance the memory performance of device including (i) the current signal ratio between its memorized state and erased state and (ii) the retention time of the signal.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1122-1124
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• 2009

Organic thin-film transistors (OTFTs) were fabricated by using the transfer patterning method. In order to remove Au pattern easily, UV-curable polymer mold was surface treated. Au source/drain (S/D) pattern was transferred to insulator-coated substrate surface. Fabricated OTFTs were compared to OTFTs using vacuum-deposited Au S/D. Additionally, transistor diodes were characterized.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.644-647
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• 2007

We have fabricated vertical type organic thin film transistor using tris-8-hydroxyquinoline aluminum $(Alq_3)$. The effects of the growth control of $Alq_3$ thin layer on the grain structure and the flatness of film surface have been investigated. In addition, we have fabricated light emitting transistor and then investigated electroluminescent properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.21-25
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• 1999

In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. In the result, we get amplitude of logic voltage of 200mV, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26ns in AC characteristic output of Ring-Oscillator connected Gate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• Current Optics and Photonics
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• v.1 no.5
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• pp.544-550
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• 2017

This simulation based study reports a novel tunable, compact, room temperature terahertz (THz) transistor source, operated on the concept of charge plasma oscillation with the capability of radiating within a terahertz gap. A vertical cavity with a quasi-periodic distributed-Bragg-reflector has been attached to a THz plasma wave transistor to achieve a monochromatic coherent surface emission for single as well as multi-color operation. The resonance frequency has been tuned from 0.5 to 1.5 THz with the variable quality factor of the optical cavity from 5 to 290 and slope efficiency maximized to 11. The proposed surface emitting terahertz transistor is able to satisfy the demand for compact solid state terahertz sources in the field of teratronics. The proposed device can be integrated with Si CMOS technology and has opened the way towards the development of silicon photonics.