• ETRI Journal
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• v.31 no.6
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• pp.749-754
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• 2009

The design and performance of an InGaAs/InP transimpedance amplifier and post amplifier for 40 Gb/s receiver applications are presented. We fabricated the 40 Gb/s transimpedance amplifier and post amplifier using InGaAs/InP heterojunction bipolar transistor (HBT) technology. The developed InGaAs/InP HBTs show a cut-off frequency ($f_T$) of 129 GHz and a maximum oscillation frequency ($f_{max}$) of 175 GHz. The developed transimpedance amplifier provides a bandwidth of 33.5 GHz and a gain of 40.1 $dB{\Omega}$. A 40 Gb/s data clean eye with 146 mV amplitude of the transimpedance amplifier module is achieved. The fabricated post amplifier demonstrates a very wide bandwidth of 36 GHz and a gain of 20.2 dB. The post-amplifier module was fabricated using a Teflon PCB substrate and shows a good eye opening and an output voltage swing above 520 mV.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.947-950
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• 2003

본 논문에서는 고속 적외선 무선 데이터통신(IrDA) 에 사용되는 트랜스임피던스 증폭기(Transimpedance Amplifier)를 설계하였다. 트랜스임피던스 증폭기는 잡음을 최소화하기 위해 PMOS 차동 구조로 설계하였으며 입력과 출력의 피드백을 통해 주위의 빛에 의해 발생되는 photocurrent 에 의한 DC 옵셋을 제거하였다 또한 공통 게이트(CG)와 Regulated Cascode Circuit (RGC)을 추가하여 대역폭(Bandwidth)을 향상시켰다. 설계한 회로는 0.25 um CMOS 공정을 이용하였으며 트랜스임피던스 이득은 200 MHz의 대역폭에서 10 KΩ (80 dBΩ )이다. 전체 전력 소비는 18 mW이다.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1737-1741
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• 2015

A multi-channel CMOS transimpedance amplifier(TIA) array is realized in a $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR systems. Each channel consists of a PIN photodiode and a feed-forward TIA that exploits an inverter input stage followed by a feed-forward common-source amplifier so as to achieve lower noise and higher gain than a conventional voltage-mode inverter TIA. Measured results demonstrate that each channel achieves $76-dB{\Omega}$ transimpedance gain, 720-MHz bandwidth, and -20.5-dBm sensitivity for $10^{-9}$ BER. Also, a single channel dissipates the power dissipation of 30 mW from a single 1.8-V supply, and shows less than -33-dB crosstalk between adjacent channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.440-448
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• 2014

A $4{\times}10$ Gb/s Transimpedance Amplifier (TIA) array is implemented in $0.13{\mu}m$ CMOS process technology, which will be used in the receiver of TWDM-PON system. A technology for bandwidth enhancement of a given $4{\times}10$ Gb/s TIA presented under inductor peaking technology and a single 1.2V power supply based low voltage design technology. It achieves 3 dB bandwidth of 7 GHz in the presence of a 0.5 pF photodiode capacitance. The trans-resistance gain is $50dB{\Omega}$, while 48 mW/ 1channel from a 1.2 V supply. The input sensitivity of the TIA is -27 dBm. The chip size is $1.9mm{\times}2.2mm$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.825-831
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• 2016

In this paper, a transimpedance amplifier based on a new DC offset cancellation (DCOC) method is proposed for WCDMA/LTE applications. The proposed method applies a sample and hold mechanism to the conventional DCOC method with a DC feedback loop. It prevents the removal of information around the DC, so it avoids signal-to-noise ratio degradation. It also reduces area and power consumption. It was designed in a $0.13{\mu}m$ deep n-well CMOS technology and drew a maximum current of 1.58 mA from a 1.2 V supply voltage. It showed a transimpedance gain of $80dB{\Omega}$, an input-referred noise current lower than 0.9 pA/${\surd}$Hz, an out-of-band input-referred 3rd-order intercept point more than 9.5 dBm, and an output DC offset lower than 10 mV. Its area is $0.46mm{\times}0.48mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.241-244
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• 2012

In this paper, three types of optical receivers are designed using a $0.35-{\mu}m$ standard CMOS technology for plastic optical fiber (POF) applications. Basic common-source transimpedance amplifier (CS-TIA), common-gate TIA (CG-TIA), and regulated-cascode TIA (RGC-TIA) are optimally designed, and their transimpedance gain (TZ gain), 3-dB bandwidth, and noise characteristics are compared and analyzed. As a result of simulations, the RGC-TIA indicates better TZ gain and 3-dB bandwidth than other topologies, and CS-TIA has the best noise performance. Each optical receiver occupies area of $0.35mm^2$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.3
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• pp.452-456
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• 2016

In this paper, a dual-channel readout amplifier array is realized in a standard $0.18{\mu}m$ CMOS technology for the applications of panoramic scan LADAR systems. Each channel consists of a PIN photodiode with 0.9 A/W responsivity and a 1.0 Gb/s readout amplifier(ROA). The proposed ROA shares the basic configuration of the previously reported feedforward TIA, except that it exploits a replica input to exclude a low pass filter(LPF), thus reducing chip area and improving integration level, and to efficiently reject common-mode noises. Measured results demonstrate that each channel achieves $70dB{\Omega}$ transimpedance gain, 829 MHz bandwidth, -22 dBm sensitivity for $10^{-9}BER$, -34 dB crosstalk between adjacent channels, and 45 mW power dissipation from a single 1.8 V supply.

• Journal of IKEEE
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• v.14 no.4
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• pp.283-290
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• 2010

This study is on the design of 10Gbps CMOS receiver circuits for fiber-optic communication. The receiver is made up of a photodiode, a transimpedance amplifier, a limiting amplifier, an equalizer, a clock and data recovery loop circuit, and a demultiplexer or demux with some auxiliary circuits including I/O circuits. Various wideband or high-speed circuit techniques are harnessed to realize a feasible, effective, and reliable receiver for a SONET fiber-optic standard, OC-192.

• Journal of the Optical Society of Korea
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• v.17 no.1
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• pp.44-49
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• 2013

A transimpedance amplifier (TIA)-optical receiver (Rx) using two intersecting active feedback system with regulated-cascode (RGC) input stage has been designed and implemented for optical interconnects. The optical TIA-Rx chip is designed in a 0.13 ${\mu}m$ CMOS technology and works up to 10 Gbps data rate. The TIA-Rx chip core occupies an area of 0.051 $mm^2$ with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/${\surd}$Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 $GHz{\Omega}/mW$.