• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.57-64
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• 2008

In this paper, we propose a system-level simulator for the performance analysis of a Solid-State Disk (SSD) in PC environment by using TLM (Transaction Level Modeling) method. Our method provides quantitative analysis for a variety of architectural choices of PC system as well as SSD. Also, it drastically reduces the analysis time compared to the conventional RTL (Register Transfer Level) modeling method. To show the effectiveness of the proposed simulator, we performed several explorations of PC architecture as well as SSD. More specifically, we measured the performance impact of the hit rate of a cache buffer which temporarily stores the data from PC. Also, we analyzed the performance variation of SSD for various NAND Flash memories which show different response time with our simulator. These experimental results show that our simulator can be effectively utilized for the architecture exploration of SSD as well as PC.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.561-562
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• 2008

In this paper, we propose a establishment of system level environment to exploit PC system with SSD (Solid State Disk) by using TLM (Transaction Level Modeling) method with SystemC language. The reason why we choose this modeling method is that it eases RTL (Register Transfer Level) modeling burdens and we can accurately estimate the performance about different architectural changes. Also, it provides simulation speed which is relatively faster than RTL modeling method. The baseline architectural platform we implemented showed that SSD's internal transfer time is a dominant factor, so we need to improve that part and it is expected to be a good simulator to measure the system's overall performance by exploiting SSD's internal architectures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.89-101
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• 2005

Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.

• Environmental and Resource Economics Review
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• v.21 no.1
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• pp.27-67
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• 2012

This paper analyzed the effect of transaction costs on the prices and trading volumes at the initial stage of emission markets and also examined how the size of the effect differs depending on the characteristics of the transactions. We built trading protocols modeling a recursive process to search the trading partner and make transactions with several behavioral assumptions considering the situations of early markets. The simulations results show that adding transaction costs resulted in reduction of trading volumes. Furthermore, the speed of reduction in trading volume to the increase of transaction costs is higher when there is scale economy. With a certain level of scale economy, the trading volumes abruptly fall down to almost zero as the transaction cost gets over a certain level. This suggests the possibility of a failed market. Since the scale economy is thought to be significant in the early stage of emission trading market, it is desirable to design a trading system that maximizes trading volumes and minimizes unit transaction costs at the outset. One of the alternatives to meet these conditions is to establish a centralized exchange and take measures to increase trading volumes.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.485-496
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• 2008

As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• The KIPS Transactions:PartD
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• v.12D no.7 s.103
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• pp.1071-1078
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• 2005

Use case modeling is a widely used technique for functional requirements analysis of business system but it is difficult to identify a use cases at the right level and use case specifications are too long and confusing. It is also hard to determine a functional decomposition Phases·s of use cases. Therefore customer doesn't understand the use cases. This paper is defining concept of the Information Structure Modeling(ISM) and analyzing business system for the customer's perspective. ISM is an efficient mechanism for analyzing user requirements and for Identifying objects in a business system using Attribute Structure Diagram which is a major tool of the ISM that describes user event. This paper is also to show how the classes are classified and derived as event-asset-transaction type in ISM. It provides a user-friendly approach to visually representing business model.

• KIEE International Transactions on Power Engineering
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• v.5A no.4
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• pp.396-402
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• 2005

In an electricity market with imperfect competition, participants devise bidding plans and transaction strategies to maximize their own profits. The market price and the quantity are concerned with the operation reserve as well as the bidding system and demand curves in an electricity market. This paper presents a market model combined by an energy market and an operating reserve market. The competition of the generation producers in the combined market is formulated as a gaming of selecting bid parameters such as intersections and slopes in bid functions. The Nash Equilibrium (NE) is analyzed by using bi-level optimization; maximization of Social Welfare (SW) and maximization of the producers' profits.

• Journal of the Korea Safety Management & Science
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• v.14 no.1
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• pp.129-136
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• 2012

This study proposes a collaboration system framework on the web service in a supply chain to implement an efficient virtual supply chain and improve an ability to fulfill received orders over a supply chain. The system based on the framework proposed in this paper plays an important role for automatic order negotiation and placing/receiving an order noticed in web service by the main system. Furthermore, it can evaluate the fulfillment of received orders over a supply chain by using the transaction results from hierarchically related vendors and establish efficient manufacturing plans. In a word, this system is the automated system for creating manufacturing plans, placing and receiving orders. A little more important main function of this system is that it has a dynamic evaluation capability about fulfillment with received orders over a supply chain, and improves the evaluation method of fulfillment ability with received orders with related to direct dealing vendors, which is a main problem in existing system. As a result, this system is able to reduce the work load of the sales and purchasing materials, production control division, to manage accurate inventory promptly, to maintain the optimal inventory level by analyzing the information of fulfillment ability with received orders, and to enhance the level of service for customers.