• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.7
• /
• pp.171-175
• /
• 1996

Gate insulator for Si field emitter is usually formed by e-beam evaporation. However, the evaported oxide requires densification for a stable process and a reduction of gate leakage which results from its Si-rich and nonstoicheiometric structure. In this study, we have developed the process technology able to densify the evaporated oxide in H$_{2}$O ambient. Using this process, we have fabricted thefield emitter array with 625 emitters per pixel, of which gate hole diameter is 1.4.mu.m, for the pixel, anode current of 14.3.mu.A was extracted at a gate bias of 100V and gate leakage was about 0.27% of the total emission current.

• Journal of Electrical Engineering and Technology
• /
• v.1 no.1
• /
• pp.114-119
• /
• 2006

This paper reports the investigation results on the leakage currents (LC) on polymeric outdoor insulators. The samples used were EPDM (ethylene prophylene diene monomer) insulators used at 20 kV distribution lines. AC voltage was applied and the LC waveforms were measured under various environmental conditions (humidity and pollution). Digital data of the LC was transferred from a digital storage oscilloscope to a computer for further analysis. The LC waveform parameters such as magnitude and harmonic content (as indicated by the total harmonic distortion (THD)) were analyzed. The experimental results showed that 3rd, 5th and 7th harmonics and higher odd harmonics were observed for symmetrical-distorted LC waveforms while for unsymmetrical-distorted LC waveforms, odd and even harmonics were observed. The LC analysis indicated that there are 5 stages of insulator conditions from normal condition up to flashover correlated with different kind of LC waveforms. The results also showed that in general the magnitude of LC was good enough to show the condition of the insulators. However, under discharge condition (for example as a result of dry band arching) the LC magnitude should be combined by the THD to show a better correlation with the insulator condition. The product between THD and LC magnitude may be used as a diagnostic parameter.

• Proceedings of the KIEE Conference
• /
• 2006.07c
• /
• pp.1465-1466
• /
• 2006

The monitoring and diagnosing technique for lightning arresters is important to assure the reliability of power supply in GIS-substation. In this paper, we described the implementation of an expert system for GIS arrester facilities. The proposed system consists of a data acquisition module (DAM), a wireless communication module, and a personal computer. The DAM detects system voltages, total leakage currents and its harmonic components, and includes an algorithm to calculate the resistive leakage current by the principle that the magnitudes of resistive leakage current are equal at the same level of the system voltage applied to the arrestor. Also, we designed a surge event detection circuit which can acquire the date, the polarity, and the amplitude of surge events. All the acquired data are transmitted after correction by many algorithms to the remote station through the ZigBee protocol. The expert system is based on the Jave Expert System Shell (JESS) and make more reliable decision by using an exclusive inference process.

• KSTLE International Journal
• /
• v.7 no.2
• /
• pp.45-50
• /
• 2006

In this paper, the leakage safety of prestressed concrete structure including the insulation panels has been analyzed using a finite element analysis just after a collapse of 9% nickel inner tank. This FEM study shows that the outer tank may contain the leaked cryogenic liquid for the time being until the primary pump in the inner tank transports stored cryogenic liquids to the nearest LNG storage tank before the outer tank is demolished. This means that the total tank thickness from the insulation panel to the outer tank system safely may retain the leaked cryogenic fluids. The FE computed results indicate that the current structure in a full containment tank is obviously enough to securing the leak-proof safety of the tank system with two primary pumps.

• Proceedings of the KIEE Conference
• /
• 2007.10c
• /
• pp.217-219
• /
• 2007

With the wide spread of direct current(DC) electric railroads in Korea, the stray current or leakage currents from negative return rails become a pending problem to the safety of nearby underground Infrastructures. The most widely used mitigation method for this interference is the stray current drainage method, which connects the underground metallic structures to the rails with diodes (polarized drainage) or thyristor (forced drainage). This method, however, inherently possesses some drawbacks such as an increase of total leakage torrents from rails, expansion of interference zone, etc. In order to resolve these drawbacks, we developed a rapid potential-controled rectifier and applied to a depot area where stray current inference is very severe. The effect of this method was analyzed from the field tell data and we suggest this method can be an excellent alternative to the drainage-bond-based mitigation methods.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.10
• /
• pp.25-34
• /
• 2002

In this paper, silicidation induced Schottky contact area was obtained using the current voltage(I-V) characteristics of shallow cobalt silicided p+-n and n+-p junctions. In reverse bias region, Poole-Frenkel barrier lowering influenced predominantly the reverse leakage current, masking thereby the effect of Schottky contact formation. However, Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n+-p junction in the forward bias region. The increase of leakage current in silicided n+-p diodes is consistent with the formation of Schottky contact via cobalt slicide penetrating into the p-substrate or near to the junction area and generating trap sites. The increase of reverse leakage current is proven to be attributed to the penetration of silicide into depletion region in case of the perimeter intensive n+-p junction. In case of the area intensive n+-p junction, the silicide penetrated near to the depletion region. There is no formation of Schottky contact in case of the p+-n junction where no increase in the leakage current is monitored. The Schottky contact amounting to less than 0.01% of the total junction was extracted by simultaneous characterization of forward and reverse characteristics of silicided n+-p diode.

• Proceedings of the KIEE Conference
• /
• 2003.10a
• /
• pp.186-188
• /
• 2003

The ZnO surge arrester is the protective device for limiting surge voltages on equipment by diverting surge current and returning the device to its original status. The occurrence of overvoltage appears in any phase to AC power supply system and it appears in mixing AC and impulse voltages, moreover because HVDC power supply system uses converter in semiconductor, it makes mixed DC and high harmonics voltages. In this study, the various mixed AC and DC voltages was made for investigating the degradation effect of ZnO arrester according to mixed voltage. As a result, the increase of DC component to mixed voltages causes the increase of resistive component of total leakage current to ZnO block. In changing V-I curve for mixed voltages, the cross-over point acts a factor as making the proper capacitor size of an equivalent circuit for ZnO block.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.11
• /
• pp.1-11
• /
• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.3
• /
• pp.139-144
• /
• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.566-569
• /
• 2001

In this paper, we investigated the electrical characteristics through DC power at manufacturing the MIS capacitor insulator AIN thin film based on reactive sputtering method. In case of deposition temperature 250$^{\circ}C$, pressure 5mTorr, total flow rate 8sccm(Ar:4sccm N2:4sccm), AIN thin film was deposited with changing DC power. As DC power increses, resistivity is observed a little increase. When AIN thin film is deposited at 100W, the result shows leakage current 10$\^$-8/A/$\textrm{cm}^2$ at 0.1MV/cm. Otherwise, In case of depositing at 150W and 200W, the result shows that the characteristic of leakage current is under 10$\^$-9//$\textrm{cm}^2$ at 0.1MV/cm. In C-V characteristic with DC power, deep depletion phenomenon is observed at inversion region in 100W and 150W. In 200W, that phenomenon, however, was showed to decrease. It shows that the hysterisis increases with being increasing DC power.