• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1714-1728
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• 2016

This paper presents improved harmonics extraction based on Adaptive Linear Neuron (ADALINE) algorithm for single phase photovoltaic (PV) shunt active power filter (SAPF). The proposed algorithm, named later as Improved ADALINE, contributes to better performance by removing cosine factor and sum of element that are considered as unnecessary features inside the existing algorithm, known as Modified Widrow-Hoff (W-H) ADALINE. A new updating technique, named as Fundamental Active Current, is introduced to replace the role of the weight factor inside the previous updating technique. For evaluation and comparison purposes, both proposed and existing algorithms have been developed. The PV SAPF with both algorithms was simulated in MATLAB-Simulink respectively, with and without operation or connection of PV. For hardware implementation, laboratory prototype has been developed and the proposed algorithm was programmed in TMS320F28335 DSP board. Steady state operation and three critical dynamic operations, which involve change of nonlinear loads, off-on operation between PV and SAPF, and change of irradiances, were carried out for performance evaluation. From the results and analysis, the Improved ADALINE algorithm shows the best performances with low total harmonic distortion, fast response time and high source power reduction. It performs well in both steady state and dynamic operations as compared to the Modified W-H ADALINE algorithm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.6
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• pp.65-72
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• 2001

This paper deals with a novel full digital control of the single-phase PWM(Pulse Width Modulation) inviter for UPS(Uninterruptible Power Supp1y). The voltage and current of output filter capacitor as a state variable are the feedback control input. In the proposed scheme a double deadbeat control consisting of minor current control loop and major voltage control loop have been developed In addition, a second order deadbeat currents control which should be exactly equal to its reference in two sampling time without error and overshoot is proposed to remove the influence of the calculation time delay. The load current prediction is achieved to compensate the load disturbance. The simulation and experimental result shows that the proposed system offers an output voltage with THD(Total Harmonic Distortion) less than 5% at a full nonlinear load.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1268-1276
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• 2016

A triode for alternating current (TRIAC) dimming light emitting diode (LED) driver, which adopts a variable switched capacitor for LED dimming and LED power regulation, is proposed in this paper. The proposed LED driver is power efficient, reliable, and long lasting because of the TRIAC switch that serves as its main switch. Similar to previous TRIAC dimmers for lamps, turn-on timing of a TRIAC switch can be controlled by a volume resistor, which modulates the equivalent capacitance of the proposed variable switched capacitor. Thus, LED power regulation against source voltage variation and LED dimming control can be achieved by the proposed LED driver while meeting the global standards for power factor (PF) and total harmonic distortion (THD). The long life and high power efficiency of the proposed LED driver make it appropriate for industrial lighting applications, such as those for streets, factories, parking garages, and emergency stairs. The detailed analysis of the proposed LED driver and its design procedure are presented in this paper. A prototype of 80 W was fabricated and verified by experiments, which showed that the efficiency, PF, and THD at V_s = 220 V are 93.8%, 0.95, and 22.5%, respectively; 65 W of LED dimming control was achieved with the volume resistor, and the LED power variation was well mitigated below 3.75% for 190 V < V_s < 250 V.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.2
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• pp.99-106
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• 2003

This paper presents a novel multilevel PWM inverter employing series-connected transformers in order to improve the waveshape of output voltage and to reduce its harmonics. The proposed 11-level inverter consists of three full-bridge inverter modules and their corresponding transformers. Among their inverter modules, one is used as PWM operation and the others as level generation. From a suitable selection of turns ratio of transformer, continuous output voltage levels were generated appearing an integral ratio to input DC source. Because of their series connection of transformers, output filter inductor is not necessary. The operational principles and analysis are explained, and it is compared with a conventional multilevel PWM inverter. The validity of the proposed system Is verified through the experimental results using a prototype.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.479-486
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• 2020

In this paper, we present a design method for improving the linearity and dynamic range of the analog current mode multiplier circuit, which is one of the key devices in an analog current mode AI processor. The proposed circuit consists of 4 quadrant translinear loops made up of NMOS transistors only, which minimizes physical mismatches of the transistors. The proposed circuit can be implemented at 117㎛ × 109㎛ in 0.35㎛ CMOS process and has a total harmonic distortion of 0.3%. The proposed analog current mode multiplier is expected to be useful as the core circuit of a current mode AI processor.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.6
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• pp.486-494
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• 2012

In this paper, we proposes the three-phase embedded Z-source inverter consisting of the three embedded Z-source converters and it's the output voltage control method. Each embedded Z-source converter can produce the bipolar output capacitor voltages according to duty ratio D such as single-phase PWM inverter. The output AC voltage of the proposed system is obtained as the difference in the output capacitor voltages of each converter, and the L-C output filter is not required. Because the output AC voltage can be stepped up and down, the boost DC converter in the conventional two-stage inverter is unnecessary. To confirm the validity of the proposed system, PSIM simulation and a DSP based experiment were performed under the condition of the input DC voltage 38V, load $100{\Omega}$, and switching frequency 30kHz. Each converter is connected by Y-connection for three-phase loads. In case that the output phase voltage is the same $38V_{peak}$ as the input DC voltage and is the 1.5 times($57V_{peak}$), the simulation and experimental results ; capacitor voltages, output phase voltages, output line voltages, inductor currents, and switch voltages were verified and discussed.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.28-34
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• 2000

In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.

• 한국태양에너지학회:학술대회논문집
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• 2012.03a
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• pp.325-330
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• 2012

A single-phase PVPCS(photovoltaic power conditioning system) that contains a single phase dc-ac inverter tends to draw an ac ripple current at twice the out frequency. Such a ripple current may shorten passive elements life span and worsen output current THD. As a result, it may reduce the efficiency of the whole PVPCS system. In this paper, the ripple current propagation is analyzed, and two methods to reduce the ripple current are proposed. Firslyt, this paper presents notch filter with IP voltage controller to reject specific current ripple in single-phase PVPCS. The notch filter can be designed that suppress just only specific frequency component and no phase delay. The proposed notch filter can suppress output command signal in the ripple bandwidth for reducing output current THD. Secondly, for reducing specific current ripple, the other method is feed-forward compensation to incorporate a current control loop in the dc-dc converter. The proposed notch filter and feed-forward compensation method have been verified with computer simulation and simulation results obtained demonstrate the validity of the proposed control scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.46-53
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• 2003

This paper describes a new linear operational transconductance amplifier (OTA) and its application to the 9th-order Bessel filter. To improve the linearity of the OTA, we employ a mobility compensation technique. The combination of the triode and the subthreshold region transistors can compensate the mobility reduction effect and make the OTA with a good linearity. The proposed OTA shows $\pm$0.32% Gm variation over the input range of $\pm$0.8-V. The total harmonic distortion (THD) was lower than -60-㏈. The 9th-order Bessel filter has been designed using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. It shows the cutoff frequency of 8-MHz and the power consumption of 65-mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.