• Journal of Advanced Research in Ocean Engineering
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• v.3 no.4
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• pp.165-173
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• 2017

This study aims at validating simulations of the forced and freely vibrating cylinders at Reynolds number of approximately 500 in order to identify the capability of the CFD code, and to establish the analysis process of the vortex-induced vibration (VIV). The direct numerical and large eddy simulations were employed to resolve the various length scales of the vortices, and the morphing technique was used to consider a motion of the circular cylinder. For the forced vibration case, both in- and anti-phase VIV processes were observed regarding the frequency ratio. Namely, when the frequency ratio approaches to unity, the synchronization/lock-in process occurs, leading to substantial increases in drag and lift coefficients. This is strongly linked with the switch in timing of the vortex formation, and this physical tendency is consistent with that of Blackburn and Henderson (J. Fluid Mech., 1999, 385, 255-286) as well as force coefficients. For the free oscillation case, the mass and damping ratio of 50.8 and 0.0024 were considered based on the study of Blackburn et al. (J. Fluid Struct., 2000, 15, 481-488) to allow the direct comparison of simulation results. The simulation results for a peak amplitude of the cylinder and a shedding mode are reasonably comparable to that of Blackburn et al. (2000). Consequently, based on aforementioned results, it can be concluded that numerical methods were successfully validated and the calculation procedure was well established for VIV analysis with reasonable results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1139-1144
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• 2008

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• The KIPS Transactions:PartB
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• v.9B no.1
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• pp.67-76
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• 2002

MP3 audio format has good quality and high compression rate ; therefore, the use of MP3 format increases. The requirement of keeping the extra information such as author and lyrics in MP3 files increases. And the tagging systems designed to meet this requirement are suggested. ID3 vl tag and Lyrics3 v2 tag are two most widely used tagging systems. But ID3 vl tag and Lyrics3 v2 tag are the last things to arrive when the file is being streamed. Therefore, users cannot get the tag information until the entire audio file is downloaded. Moreover information synchronized with audio stream may lose its feature. In this paper, a system searching and playing audio files based on tag information in MP3 files is implemented. This system solves the problem that the tag information is ignored when an MP3 files is played on internet. An audio object is described in an XML document, and timing and synchronization between elements in that In document is provided in HTML+TIME style using XSL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1161-1167
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• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.121-126
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• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1727-1734
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• 2011

In this paper, a position control scheme of the ink droplet is presented for the high image quality and print speed ink jet printer. The proposed scheme estimates the impact position and compensates it by control of the jet strobe time based on the dynamic equations describing the moving trajectory of the ejected ink droplet. Compared to the conventional jet strobe control which is based on the simple synchronization with the position signal of the ink jet nozzle, the proposed control scheme provides more accurate impact position control while the carrier is moving with accelerated or decelerated speed as well as steady state speed with fluctuations. The availability of printing during the acceleration and deceleration states of the carrier moving enables the print speed up and the frame size down which means the cost down.

• Fisheries and Aquatic Sciences
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• v.21 no.9
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• pp.23.1-23.8
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• 2018

Background: Russian sturgeon (Acipenser gueldenstaedtii) is an emerging candidate species in the Korean aquaculture domain owing to its highly valued caviar. Although the embryonic development of this species was previously described, the complete image data on the morphological differentiation of developing embryos have not been yet fully available. Further, with the viewpoint of larval production in hatchery, the effects of temperature on embryonic viability and the temporal window of hatching event have not been extensively studied. Hence, the objective of this study was to provide a complete set of photographic image data on the embryogenesis and also to examine the effects of incubation temperatures on embryonic viability and hatching event in farm-bred Russian sturgeon. Results: Typical characteristics of embryonic development including uneven, holoblastic cleavages with unequal blastomeres, followed by the formation of germ layer, neurulation, and organogenesis until hatching, were documented. Under different temperature conditions (12, 16, or $20^{\circ}C$), viability of embryos incubated at $12^{\circ}C$ was significantly lower as relative to those of 16 and $20^{\circ}C$ incubated embryos. Hatchability of embryos was higher, and the timing of hatching event was more synchronized at $20^{\circ}C$ than at 12 and $16^{\circ}C$. Conclusion: Data from this study suggest that the incubation of Russian sturgeon embryos at $20^{\circ}C$ would be desirable in the hatchery practice with respect to the good hatchability of embryos and the synchronization of hatching events. Additionally, the updated image data for complete embryonic development could be a useful reference guide for not only developmental researches but also artificial propagation of Russian sturgeon in farms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.1-7
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• 2000

Generally, one-dimensional fiber optic code-division multiple-access(CDMA) system is encoded and decoded using optical orthogonal codes(OOC’s), where two-dimensional fiber optic CDMA system uses optical orthogonal signature pattern codes(OOSPC’s) for parallel data link process. The OOSPC’s should have good autocorrelation and cross-correlation properties. However, if timing information or synchronization of OOSPC’s can be obtained by other means, the property of autocorrelation may not be restricted and we can increase the number of pattern codes. In this paper we introduce the fiber optic CDMA system for parallel transmission of two-dimensional data and investigate methods of generation of two-dimensional pattern codes. The probability density function of interference noise is calculated in interfering OOSPC’s of the users and the corresponding bit error rate is derived.. We compare each OOSPC’s by plotting bit error rate versus threshold values and the number of simultaneous users, from the result, we propose the optimal OOSPC’s conditions for the parallel transmission of two-dimensional data.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.70-77
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• 2008

On the wireless sensor network MAC protocols, one of main issues is energy enciency. Since several asynchronous wireless sensor network MAC protocols with short preamble sampling scheme can be operated without setting the timing synchronization among neighbor nodes, it consumes a little energy for maintaining protocols. However, each node encounters either preamble or data overhearing problem, because each node wakes up in a different time and must check whether the frame is being sent to itself or not. To solve this overhearing problem, we newly propose B-MAC++ that can reduce the overhearing energy consumption by using short preambles with destination address and payload length. from simulation results, we show that the proposed B-MAC++ has advantageous in terms of power consumption efficiency over other asynchronous wireless sensor network MAC protocols.