• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.175-175
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• 1999

Circumventing problems lying in the conventional lithographic techniques, we devised a new method for the fabrication of nanometer scale metal wires inspired by the unique characteristics of carbon nanotubes (CNTs). Since carbon nanotubes could act as masks when CNT-coated thin Au/Ti layer on a SiO2 surface was physically etched by low energy argon ion bombardment 9ion milling), Au/Ti nano-wires were successfully formed just below the CNTs exactly duplicating their lateral shapes. Cross-sectional analysis by transmission electron microscopy revealed that the edge of the metal wire was very sharply developed indicating the great difference in the milling rates between the CNTs and the metal layer as well as the good directionality of the ion milling. We could easily find a few nanometer-wide Au/Ti wires among the wires of various width. After the formation of nano-wires, the CNTs could be pushed away from the metal nano-wire by atomic force microscopy, The lateral force for the removal of the CNTs are dependent upon the width and shape of the wires. Resistance of the metal nano-wires without the CNTs was also measured through the micro-contacts definted by electron beam lithography. since this CNT-based lithographic technique is, in principle, applicable to any kinds of materials, it can be very useful in exploring the fields of nano-science and technology, especially when it is combines with the CNT manipulation techniques.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.7
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• pp.514-520
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• 1999

Ferroelectric PZT(30/70)/PZT(70/30) heterolayered thin films were fabricated by spin-coating method on the $Pt/Ti/SiO_2Si$ substrate alternately using(30/70) and PZT(70/30) alkoxide solutions prepared by sol-coating method. The coating and heating procedure was repeated six times to form PZT heterolayered films, and thickness of the film obtained by one-times drying/sintering process was about 40-50 nm. All PZT heterolayered films, showed dense and homogeneous structure without the presence of rosette sturctrue. The relative dielectric constant, remanent polarization and leakage current density of PZT heterolayered films were superior to those of single composition PZT(30/70) and PZT(70/30) films, and those values for the PZT-6 film were 975, $21 \muC/cm^2\; and\; 8\times10^{-9}\; A/cm^2$, respectively. And the PZT-6 heterolayered film showed fairly good fatigue characteristics of remanent polarization and coercive field after application of $10^8$ switching cycles.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.171-171
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• 2007

Dysprosium-doped bismuth titanate (BDT) thin films were successfully deposited on Pt(111)/Ti/$SiO_2$/Si(100) substrates by liquid delivery MOCVD process and their structural and ferroelectric properties were characterized. Fabricated BDT thin films were found to be random orientations, which were confirmed by X-ray diffraction experiment and scanning electron microscope analysis. The crystallinity of the BDT films was improved and the average grain size increased as the crystallization temperature increased from 600 to $720^{\circ}C$ at an interval of $40^{\circ}C$. The BDT thin film annealed at $720^{\circ}C$ showed a large remanent polarization (2Pr) of $52.27\;{\mu}C/cm^2$ at an applied voltage of 5V. The BDT thin film exhibits a good fatigue resistance up to $1.0{\times}10^{11}$ switching cycles at a frequency of 1 MHz with applied pulse of ${\pm}5\;V$. These results indicate that the randomly oriented BDT thin film is a promising candidate among ferroelectric materials useti비 in lead-free nonvolatile ferroelectric random access memory applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.5
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• pp.499-503
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• 2022

La_0.7Sr_0.3MnO₃ precursor solution were prepared by a sol-gel method. La_0.7Sr_0.3MnO₃ thin films were fabricated by a spin-coating method on a Pt/Ti/SiO₂/Si substrate. Structural and electrical properties with the variation of sintering temperature were measured. All specimens exhibited a polycrystalline orthorhombic crystal structure, and the average thickness of the specimens coated 6 times decreased from about 427 nm to 383 nm as the sintering temperature increased from 740℃ to 830℃. Electrical resistance decreased as the sintering temperature increased. In the La_0.7Sr_0.3MnO₃ thin films sintered at 830℃, electrical resistivity, TCR, B-value, and activation energy were 0.0374 mΩ·cm, 0.316%/℃, 296 K and 0.023 eV, respectively.

• Korean Journal of Materials Research
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• v.19 no.7
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• pp.349-355
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• 2009

Metal thin film patterns on a LTCC substrate, which was connected through inner via and metal paste for electrical signals, were formed by a screen printing process that used electric paste, such as silver and copper, in a conventional method. This method brought about many problems, such as non uniform thickness in printing, large line spaces, and non-clearance. As a result of these problems, it was very difficult to perform fine and high resolution for high frequency signals. In this study, the electric signal patterns were formed with the sputtered metal thin films (Ti, Cu) on an LTCC substrate that was coated with protective oxide layers, such as $TiO_2$ and $SiO_2$. These electric signal patterns' morphology, surface bonding strength, and effect on electro plating were also investigated. After putting a sold ball on the sputtered metal thin films, their adhesion strength on the LTCC substrate was also evaluated. The protective oxide layers were found to play important roles in creating a strong design for electric components and integrating circuit modules in high frequency ranges.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.9-17
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• 2011

Nano-composite solders have been studied to improve the properties of Pb-free solder joints. The nanoparticles in the composite solders were carbon nanotubes(CNTs), metals (Ag, Ni, Cr, etc.), ceramics (SiC, $ZrO_2$, $TiB_2$, etc.). To fabricate the nano-composite solders, mechanical mixing methods and in-situ fabrication method has been used for well-dispersed nano phase. The characteristic properties of the nano-composite solders were high creep resistance, low undercooling, low IMC growth rate and fine microstructures. More researches on the nano-composite solders are required to improve the processibility and the reliability of the nano-composite solder joints.

• Applied Microscopy
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• v.42 no.3
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• pp.164-173
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• 2012

The relaxor ferroelectric feature in lead-free perovskite oxides, where the dipoles are randomly oriented and they can be feasibly aligned parallel to the external bias, is attracting lots of attention in the field of piezoelectric materials science, since it is one of candidates to replace the toxic lead-based materials that are still being commercially used. However, the origin of relaxor characteristic and its related atomic structure are still ambiguous. In this study, $Na_{1/2}Bi_{1/2}TiO_3$, chosen as a model relaxor system, was found to exhibit a cationic-disordered atomic structure; and furthermore the nonpolar atomic structure and its related oxygen tilting were ascertained via annular bright field imaging skill. We also found that this cationic disordering gives rise to the local formation of atomic vacancies.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.69-69
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• 2011

다이아몬드는 절연 물질이지만, 합성 다이아몬드를 생성할 때 결정 내에 도핑(doping) 과정을 통해 불순물을 혼입함으로써 반도체 성질을 가지게 된다. 본 연구에서는 마이크로웨이브 CVD 장치를 이용하여 다이아몬드 박막의 생성 조건을 최적화하고 여기에 다이아몬드 박막 생성시 디보란(Diborane, B2H6)을 주입하여 전기적 특성을 갖는 보론-도핑 된 다이아몬드 박막을 생성하였다. 실험 조건으로는 방전전력 1.4 Kw, 진공압력 40 Torr의 상태에서 디보란의 주입량을 각각 다르게 하여 실험을 진행하였다. 이 때 사용된 기판으로는 전기적 특성이 서로 다른 사파이어($Al_2O_3$), Si, Ti 기판을 사용하여 박막과 기판과의 연관성도 조사하였다. 각각의 보론-도핑 농도와 기판에 따른 다이아몬드 결정구조를 Micro Raman, SEM으로 분석하였고, 다이아몬드 박막의 I-V특성을 통해 다이아몬드의 전기적 특성을 조사하였다.

• KIEE International Transactions on Electrophysics and Applications
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• v.11C no.2
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• pp.18-22
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• 2001

The thin films of high permitivity in ferroelectric materials using a capacitor are applied to DRAMs and FRAMs. (Ba, Sr)TiO$_3$ thin as ferroelectric materials were prepared by the sol-gel method and made by spin-coating on the Pt/Sio$_2$/Si substrate at 4,000 [rpm] for 10 seconds. The structural characteristics of the surface were analyzed by fractal dimension. The thickness of BST ceramics thin films was about 260∼280 [nm]. The property of the leakage current was stable with 10-9∼10-11[A] when the applied voltage was 0∼3[V]. BST thin films ha low leakage current properties when fractal dimension was low and a coating area was high.