• Proceedings of the KIEE Conference
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• 2009.04a
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• pp.27-29
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• 2009

본 연구에서는 Titanate Nanotube (TNT)를 LBL-SA (layer-by-layer self-assembling) method을 이용하여 전기변색 (electrochromism device, ECD) 소자에 적용하고자 하였다. TNT 분말은 10M NaOH와 $TiO_2$를 혼합한 후 autoclave에서 130$^{\circ}C$, 48시간 동안 수열합성하여 제조하였다. 주사전자현미경 (SEM)으로 TNT 분말의 형상을 관찰한 결과, 직경 20$\sim$30nm, 길이 500$\sim$600nm의 튜브 형상을 나타내었으며, X-선 회절시험 (XRD) 결과 층상구조로 확인되었다. 코팅 물질의 표면 전하를 이용한 LBL-SA method에 적용시키기 위해 수용액 중에서 TNT 입자 표면 전하를 TBAOH (tetrabutylammonium hydroxide)를 적정하여 제타 전위 값이 -40mV로 최대가 되도록 하였으며, 이때 pH 값은 9로 나타났다. 2전극 시스템을 이용하여 cycle voltammetry를 측정한 결과, -0.5$\sim$-1.5V 영역에서 산화환원전위 피크가 뚜렷하게 나타났으며, 짙은 갈색으로 변색되는 것을 확인하였다. 본 연구 결과로서 TNT 박막은 전기를 인가하였을 때 n-type 반도체 성질을 갖는 것으로 나타났으며, 앞으로 display 연구 분야에 적용할 수 있을 것으로 주목된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.98-98
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• 2013

완전화 박막이란 사용자가 원하는 용도에 맞게 최적의 성능을 구현하도록 제조된 박막을 의미하며 금속이나 화합물 박막을 제조하되 각종 구조 제어 Tool이나 증착 공정을 변화시켜 나노화와 다층화 또는 치밀화를 통해 구현될 수 있다. 최근 고성능의 증착 및 제어 Tool이 개발되고 빗각증착(Oblique Angle Deposition)이나 스침각 증착(Glancing Angle Deposition) 방법 등의 기술이 개발되면서 사용자 목적에 최적인 박막 소재를 제공하여 User-friendly한 응용을 위한 연구개발이 활발히 진행되고 있다. 완전화 박막 제조에 대한 시도는 1990년대에 일본에서 시작되었다. 일본에서는 산학연이 공동으로 참여하는 NEDO 프로그램을 통해 경질코팅을 이용한 Protective Layer를 제조하여 차단 방식에 의한 내식성 구현 연구를 수행하였다. 유럽에서는 제 7차 European Framework Program (7th FT)을 통해 2007년부터 CORRAL (Corrosion Protection with Perfect Atomic Layer) 프로젝트를 만들어 완전화 박막 연구를 진행하고 있다. 상기 프로젝트는 얇은 자연 산화막이 Bulk의 부식을 방지해주는 것에 착안하여 HIPIMS나 Filtered Arc 또는 ALD 공정을 이용하여 자연 산화막과 유사한 Defect-free 산화막을 제조하여 Barrier형 내식성 박막을 구현하는 것을 목표로 하고 있다. 본 연구에서는 완전화 박막 구현을 위한 연구동향을 파악하고 완전화 박막 제조를 위한 기술적 과제와 몇 가지의 시도에 대한 기초 연구 자료를 소개한다.

• Journal of the Korean Applied Science and Technology
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• v.20 no.2
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• pp.148-153
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• 2003

Electron transfer through an Langmuir-Blodgett(LB) monolayer film sandwiched between metal electrodes. We used an eicosanoic acid material and the material was very famous as a thin film insulating material. Eicosanoic acid monolayer was deposited by Langmuir-Blodgett(LB) technique and a subphase was a $CdCl_2$ solution as a 2${\times}10^{-4}$ mol/L. Also we used a bottom electrode as an Al/$Al_2O_3$ and a top electrode as a Al and Ti/Al. Here, the $Al_2O_3$ on the bottom electrode was deposited by thermal evaporation method. The $Al_2O_3$ layer was acted on a tunneling barrier and insulating layer in tunnel diode. It was found that the proper transfer surface pressure for film deposition was 25 mN/m and the limiting area per molecule was about 24 ${\AA}^2$/molecule. When the positive and negative bias applied to the molecular device, the behavior shows that a tunnel switching characteristics. This result were analyzed regarding various mechanisms.

• Journal of the Korean Ceramic Society
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• v.35 no.8
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• pp.827-835
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• 1998

Blanket Copper films were chemically vapor deposited on six kinds for substrates for scrutinizing the change of characteristics induced by the difference of substrates and seeding layers. Both TiN/Si and {{{{ { SiO}_{2 } }}/Si wafers were used as-recevied and with the Cu-seeding layers of 40${\AA}$ and 160${\AA}$ which were produced by sputtering The CVD processes were exectued at the deposition temperatures between 130$^{\circ}C$ and 260$^{\circ}C$ us-ing (hfc)Cu(VTMS) as a precursor. The deposition rate of 40$^{\circ}C$ Cu-seeded substrates was higher than that of other substrates and especially in seeded {{{{ { SiO}_{2 } }}/Si substrate because of the incubation period reducing in-duced by seeding layer at the same deposition time and temperature. The resistivity of 160${\AA}$ Cu seeded substrate was lower then that of 40 ${\AA}$ because the nucleation and growth behavior in Cu-island is different from the behavior in {{{{ { SiO}_{2 } }} substrate due to the dielectricity of {{{{ { SiO}_{2 } }}.

• Korean Journal of Materials Research
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• v.32 no.6
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• pp.293-300
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• 2022

This study investigated a graded-refractive-index (GRIN) coating pattern capable of improving the light extraction efficiency of GaN light-emitting diodes (LEDs). The planar LEDs had total internal reflection thanks to the large difference in refractive index between the LED semiconductor and the surrounding medium (air). The main goal of this paper was to reduce the trapped light inside the LED by controlling the refractive index using various compositions of (TiO₂)_x(SiO₂)_1-x in GRIN LEDs consisting of five dielectric layers. Several types of multilayer LEDs were simulated and it was determined the transmittance value of the LEDs with many layers was greater than the LEDs with less layers. Then, the specific ranges of incident angles of the individual layers which depend on the refractive index were evaluated. According to theoretical calculations, the light extraction efficiency (LEE) of the five-layer GRIN is 25.29 %, 28.54 % and 30.22 %, respectively. Consequently, the five-layer GRIN LEDs patterned enhancement outcome LEE over the reference planar LEDs. The results suggest the increased light extraction efficiency is related to the loss of Fresnel transmission and the release of the light mode trapped inside the LED chip by the graded-refractive-index.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.21-25
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• 2017

In this study, we have fabricated Schottky barrier diodes (SBD) on single-crystal ${\beta}-Ga_2O_3$ semiconductor that has received much attention for use in next-generation power devices. The SBD had a Pt/Ti/Au Schottky contact on a $2{\mu}m$ Sn-doped low concentration N-type epitaxial layer. The fabricated device exhibited a breakdown voltage of > 180 V, a specific on-resistance of $1.26m{\Omega}{\cdot}cm^2$, and forward current densities of $77A/cm^2$ at 1 V and $473A/cm^2$ at 1.5 V, which proved the potential for use in power device fabrication.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.279-279
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• 2011

나노 입자를 이용한 비휘발성 메모리 소자의 전기적 특성 향상을 위하여 일함수가 Si 보다 큰 금속, 금속산화물, 금속 실리사이드 나노입자를 이용한 다양한 형태의 메모리 구조가 제안되어져 왔다.[1] 특히 이와 같은 나노 부유 게이트 구조에서 터널 절연막의 구조를 소자의 동작 속도를 결정하는데 이는 터널링 되어 주입되는 전자의 확률에 의존하기 때문이다. 양자 우물에 국한된 전하가 누설되지 않으면서 주입되는 전자의 터널링 확률을 증가시키기 위하여, dielectric constant 와 barrier height를 고려한 다양한 구조의 터널 절연막의 형태가 제안 되었다.[2-3] 특히 낮은 전계에서도 높은 터널링 확률은 메모리 소자의 동작 속도를 향상시킬 수 있다. 본 연구에서는 n형 Si 기판위에 Si3N4 및 HfAlO를 각각 1.5 nm 및 3 nm 로 atomic layer deposition 방법으로 증착하였으며 3~5 nm 지름을 가지는 $TiSi_2$ 및 $WSi_2$ 나노 입자를 형성한 후 컨트롤 절연막인 $SiO_2$를 ultra-high vacuum sputtering을 사용하여 20 nm 두께로 형성 하였다. 마지막으로 $200{\mu}m$ 지름을 가지는 Al 전극을 200 nm 두께로 형성하여 나노 부유 게이트 커패시터를 제작하였다. 제작된 소자는 Agilent E4980A precision LCR meter 및 HP 4156A precision semiconductor parameter analyzer 를 사용하여 전기용량-전압 및 전류-전압 특성분석을 하여 전하저장 특성 및 제작된 소자의 터널링 특성을 확인 하여 본 연구를 통하여 제작된 나노 부유 게이트 커패시터 구조가 메모리 소자응용이 가능함을 확인하였다.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.387-387
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• 2013

Currently, the flash memory and the dynamic random access memory (DRAM) have been used in a variety of applications. However, the downsizing of devices and the increasing density of recording medias are now in progress. So there are many demands for development of new semiconductor memory for next generation. Magnetic random access memory (MRAM) is one of the prospective semiconductor memories with excellent features including non-volatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM is composed of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack consists of various magnetic materials, metals, and a tunneling barrier layer. Recently, MgO thin films have attracted a great attention as the prominent candidates for a tunneling barrier layer in the MTJ stack instead of the conventional Al2O3 films, because it has low Gibbs energy, low dielectric constant and high tunneling magnetoresistance value. For the successful etching of high density MRAM, the etching characteristics of MgO thin films as a tunneling barrier layer should be developed. In this study, the etch characteristics of MgO thin films have been investigated in various gas mixes using an inductively coupled plasma reactive ion etching (ICPRIE). The Cl2/Ar, CH3OH/Ar, and CH4/Ar gas mix were employed to find an optimized etching gas for MgO thin film etching. TiN thin films were employed as a hard mask to increase the etch selectivity. The etch rates were obtained using surface profilometer and etch profiles were observed by using the field emission scanning electron microscopy (FESEM).

• The Korean Journal of Ceramics
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• v.7 no.1
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• pp.36-40
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• 2001

In order to fabricate uncooled IR sensors for pyroelectric applications, multilayered thin films of Pt/PbTiO$_3$/Pt/Ti/Si$_3$N$_4$/SiO$_2$/Si and thermally isolating membrane structures of square-shaped/cantilevers-shaped microstructures were prepared. Cavity was also fabricated via direct silicon wafer bonding and etching technique. Metallic Pt layer was deposited by ion beam sputtering while PbTiO$_3$ thin films were prepared by sol-gel technique. Micromachining technology was used to fabricate microstructured-membrane detectors. In order to avoid a difficulty of etching active layers, silicon-nitride membrane structure was fabricated through the direct bonding and etching of the silicon wafer. Although multilayered thin film deposition and device fabrications were processed independently, these could b integrated to make IR micro-sensor devices.