• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1910-1912
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• 1999

This paper was described electrical characteristics of Metal/GaN contact for application of GaN thin films. The lowest contact resistivity was $1.7\times10^{-7}[\Omega-cm^2]$ at Ti/Al Structure. Mean while, GaN MESFETs have been fabricated with a 250 nm thick channel on a high resistivity GaN layer grown by GAIVBE system. For a gate-source diode reverse bias of 35 V, the gate leakage current was $120{\mu}A$. From the data, we estimate the transconductance for our GaN MESFET to be 25 mS/mm.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.211-212
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• 2010

GaN 기반의 상부발광형 LED는 동작되는 동안 생기는 전기적 단락, 그리고 칩 위의 p-형 전극과 n-형 전극 사이에 생기는 누설전류 및 신뢰성 확보를 위하여 칩 표면에 passivation 층을 형성하게 된다. SiO2, Si3N4와 같은 passivation layers는 일반적으로 PECVD (Plasma Enhanced Chemical Vapor Deposition)공정을 이용한다, 하지만 이는 공정 특성상 plasma로 인한 damage가 유발되기 때문에 표면 누설 전류가 증가 한다. 이로 인해 forward voltage와 reverse leakage current의 특성이 저하된다. 본 실험에서는 원자층 단위의 박막 증착으로 인해 PECVD보다 단차 피복성이 매우 우수한 PEALD(Plasma Enhanced Atomic Layer Deposition)공정을 이용하여 Al2O3 passivation layer를 증착한 후, 표면 누설전류와 빛의 출력 특성에 대해서 조사해 보았다. PSS (patterned sapphire substrate) 위에 성장된 LED 에피구조를 사용하였고, TCP(Trancformer Copled Plasma)장비를 사용하여 에칭 공정을 진행하였다. 이때 투명전극을 증착하기 위해 e-beam evaporator를 사용하여 Ni/Au를 각각 $50\;{\AA}$씩 증착한 후 오믹 특성을 향상시키기 위하여 $500^{\circ}C$에서 열처리를 해주었다. 그리고 Ti/Au($300/4000{\AA}$) 메탈을 사용하여 p-전극과 n-전극을 형성하였다. Passivation을 하지 않은 경우에는 reverse leakage current가 -5V 에서 $-1.9{\times}10-8$ A 로 측정되었고, SiO2와 Si3N4을 passivation으로 이용한 경우에는 각각 $8.7{\times}10-9$과 $-2.2{\times}10-9$로 측정되었다. Fig. 1 에서 보면 알 수 있듯이 5 nm의 Al2O3 film을 passivation layer로 이용할 경우 passivation을 하지 않은 경우를 제외한 다른 passivation 경우보다 reverse leakage current가 약 2 order ($-3.46{\times}10-11$ A) 정도 낮게 측정되었다. 그 이유는 CVD 공정보다 짧은 ALD의 공정시간과 더 낮은 RF Power로 인해 plasma damage를 덜 입게 되어 나타난 것으로 생각된다. Fig. 2 에서는 Al2O3로 passivation을 한 소자의 forward voltage가 SiO2와 Si3N4로 passivation을 한 소자보다 각각 0.07 V와 0.25 V씩 낮아지는 것을 확인할 수 있었다. 또한 Fig. 3 에서는 Al2O3로 passivation을 한 소자의 output power가 SiO2와 Si3N4로 passivation을 한 소자보다 각각 2.7%와 24.6%씩 증가한 것을 볼 수 있다. Output power가 증가된 원인으로는 향상된 forward voltage 및 reverse에서의 leakage 특성과 공기보다 높은 Al2O3의 굴절률이 광출력 효율을 증가시켰기 때문인 것으로 판단된다.

• The Journal of Korean Academy of Prosthodontics
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• v.44 no.6
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• pp.740-750
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• 2006

Statement of problems. In an attempt to reduce screw loosening, dry lubricant coatings such as pure gold or tefron have been applied to the abutment screw. However, under repeated tightening and loosening procedures, low wear resistance and adhesion strength of coating material produced free particles on the surface of abutment screw and increased frictional resistance resulting in screw tightening problems. Purpose. The aim of this study was to compare friction coefficient, adhesion strength, vickers hardness and evaluate coating surface of titanium alloy specimens coated with TiN(titanium nitride), ZrN(zirconium nitride) and WC(tungsten carbide). Material and method. Titanium alloy(Ti-6Al-4V) discs of 12mm in diameter and 1mm in thickness divided into 4 groups. TiN, ZrN and WC was coated for the specimens of 3 groups respectively, and those of 1 group were not coated. Each group was made up of 4 specimens. In this study, sputtering method was used among the PVD(Physical Vapor Deposition) techniques available for TiN, ZrN and WC coatings. Friction coefficient, adhesion strength, vickers hardness and coating surface of 4 groups were measured. Results. 1. For all three coating conditions, friction coefficient was significantly decreased. Especially, ZrN coated surface showed the lowest value. $TiN(0.39{\pm}0.02)$, $ZrN(0.24{\pm}0.01)$, $WC(0.31{\pm}0.03)$. 2. TiN coating showed the highest adhesion strength, however ZrN coating had the lowest value. $TiN(25.3N{\pm}1.6)$, $ZrN(14.8N{\pm}0.6)$, $ WC(18.4N{\pm}0.7)$. 3. Vickers hardness of all three coatings was remarkably increased as compared with that of none coated specimen. TiN coating had the highest Vickers hardness, however WC coating showed the lowest value. $TiN(1865.2{\pm}33.8)$, $ZrN(1814.4{\pm}18.6)$, $WC(1008.5{\pm}35.9)$. 4. The ZrN or WC coated specimen showed a homogeneous and smooth surface, however the rough surface with defects was observed for TiN coating. Conclusions. When TiN, ZrN and WC coating applied to the abutment screw, frictional resistance would be reduced, as a result, the greater preload and prevention of the screw loosening could be expected.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.166-166
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• 2010

Recently, TFTs based on amorphous oxide semiconductors (AOSs) such as ZnO, InZnO, ZnSnO, GaZnO, TiOx, InGaZnO(IGZO), SnGaZnO, etc. have been attracting a grate deal of attention as potential alternatives to existing TFT technology to meet emerging technological demands where Si-based or organic electronics cannot provide a solution. Since, in 2003, Masuda et al. and Nomura et al. have reported on transparent TFTs using ZnO and IGZO as active layers, respectively, much efforts have been devoted to develop oxide TFTs using aforementioned amorphous oxide semiconductors as their active layers. In this thesis, I report on the performance of thin-film transistors using amorphous indium gallium zinc oxides for an active channel layer at room temperature. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium gallium zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium gallium zinc oxide was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 1.5V and an on/off ration of > $10^9$ operated as an n-type enhancement mode with saturation mobility with $9.06\;cm^2/V{\cdot}s$. The devices show optical transmittance above 80% in the visible range. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium gallium zinc oxides for an active channel layer were reported. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.438-439
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• 2013

Microelectronic devices의 접촉저항의 향상을 위해 Metal silicides의 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 지난 수십년에 걸쳐, Ti silicide, Co silicide, Ni silicide 등에 대한 개발이 이루어져 왔으나, 계속적인 저저항 접촉 소재에 대한 요구에 의해 최근에는 Rare earth silicide에 관한 연구가 시작되고 있다. Rare-earth silicide는 저온에서 silicides를 형성하고, n-type Si과 낮은 schottky barrier contact (~0.3 eV)를 이룬다. 또한, 비교적 낮은 resistivity와 hexagonal AlB2 crystal structure에 의해 Si과 좋은 lattice match를 가져 Si wafer에서 high quality silicide thin film을 성장시킬 수 있다. Rare earth silicides 중에서 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 낮은 schottky barrier 응용에서 쓰이고 있다. 이로 인해, n-channel schottky barrier MOSFETs의 source/drain으로써 주목받고 있다. 특히 ytterbium과 molybdenum co-deposition을 하여 증착할 경우 thin film 형성에 있어 안정적인 morphology를 나타낸다. 또한, ytterbium silicide와 마찬가지로 낮은 면저항과 electric work function을 갖는다. 그러나 ytterbium silicide에 molybdenum을 화합물로써 높은 농도로 포함할 경우 높은 schottky barrier를 형성하고 epitaxial growth를 방해하여 silicide film의 quality 저하를 야기할 수 있다. 본 연구에서는 ytterbium과 molybdenum의 co-deposition에 따른 silicide 형성과 전기적 특성 변화에 대한 자세한 분석을 TEM, 4-probe point 등의 다양한 분석 도구를 이용하여 진행하였다. Ytterbium과 molybdenum을 co-deposition하기 위하여 기판으로 $1{\sim}0{\Omega}{\cdot}cm$의 비저항을 갖는 low doped n-type Si (100) bulk wafer를 사용하였다. Native oxide layer를 제거하기 위해 1%의 hydrofluoric (HF) acid solution에 wafer를 세정하였다. 그리고 고진공에서 RF sputtering 법을 이용하여 Ytterbium과 molybdenum을 동시에 증착하였다. RE metal의 경우 oxygen과 높은 반응성을 가지므로 oxidation을 막기 위해 그 위에 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, 진공 분위기에서 rapid thermal anneal(RTA)을 이용하여 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium silicides를 형성하였다. 전기적 특성 평가를 위한 sheet resistance 측정은 4-point probe를 사용하였고, Mo doped ytterbium silicide와 Si interface의 atomic scale의 미세 구조를 통한 Mo doped ytterbium silicide의 형성 mechanism 분석을 위하여 trasmission electron microscopy (JEM-2100F)를 이용하였다.

• Journal of the Korean Ceramic Society
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• v.35 no.7
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• pp.647-647
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• 1998

(La,Sr)CoO3/Pb(Zr,Ti)O3/(La,Sr)CoO3 (LSCO) heterostructures have been grown on LaAlO3 substrates by pulsed laser deposition (PLD) to investigate asymmetric polarization of Pb(Zr,Ti)O3 (PZT) thin flims with different electrode configuration. P-V hysteresis loop of LSCO/PZT/LSCO was symmetric. However, LaCoO3 (LCO_/PZT/LSCO showed a largely asymmetric P-V hystersis loop and large relaxation of the remanent polarization at the negatively poled state, which means that the negatively poled state was unstable. On the other hand, LSCO/PZT/LCO exhibited large relaxation of the positively poled state. The asymmetric behavior of the polarized states implies the presence of an interal electric firld inside the PZT layer. It is suggested that internal electric field is caused by built-in voltages at LCO/PZT and LSCO/PZT interfaces. The built-in voltages at LCO/PZT and CSCO/PZT interfaces were 0.6 V and -0.12 V, respectively.

• Korean Journal of Materials Research
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• v.14 no.2
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• pp.133-140
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• 2004

We carried out anodic aluminum oxide (AAO) on a Si and a sapphire substrate. For anodic oxidation of Al two types of specimens prepared were Al(0.5 $\mu\textrm{m}$)!Si and Al(0.5 $\mu\textrm{m}$)/Ti(0.1 $\mu\textrm{m}$)$SiO_2$(0.1 $\mu\textrm{m}$)/GaN(2 $\mu\textrm{m}$)/Sapphire. Surface morphology of Al film was analyzed depending on the deposition methods such as sputtering, thermal evaporation, and electron beam evaporation. Without conventional electron lithography, we obtained ordered nano-pattern of porous alumina by in- situ process. Electropolishing of Al layer was carried out to improve the surface morphology and evaluated. Two step anodizing was adopted for ordered regular array of AAO formation. The applied electric voltage was 40 V and oxalic acid was used as an electrolyte. The reference electrode was graphite. Through the optimization of process parameters such as electrolyte concentration, temperature, and process time, a regular array of AAO was formed on Si and sapphire substrate. In case of Si substrate the diameter of pore and distance between pores was 50 and 100 nm, respectively. In case of sapphire substrate, the diameter of pore and distance between pores was 40 and 80 nm, respectively

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.337-341
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• 2014

For various additives doped-$VO_2$ critical temperature sensors using the nature of semiconductor to metal transition, the crystallinity, microstructure, and temperature vs. resistance characteristics were systematically investigated. As a starting material of $VO_2$ sensor, vanadium pentoxide ($V_2O_5$) powders were used, and CaO, SrO, $Bi_2O_3$, $TiO_2$, and PbO dopants were used, respectively. The $V_2O_5$ powders with dopants were mixed with a vehicle to form paste. This paste was silk screen-printed on $Al_2O_3$ substrates and then $V_2O_5$-based thick films were heat-treated at $500^{\circ}C$ for 2 hours in $N_2$ gas atmosphere for the reduction to $VO_2$. From X-ray diffraction analysis, $VO_2$ phases for pure $VO_2$, and CaO and SrO-doped $VO_2$ thick films were confirmed and their grain sizes were 0.57 to $0.59{\mu}m$. The on/off resistance ratio of the $VO_2$ sensor in phase transition temperature range was $5.3{\times}10^3$ and that of the 0.5 wt.% CaO-doped $VO_2$ sensor was $5.46{\times}10^3$. The presented critical temperature sensors could be commercialized for fire-protection and control systems.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.258-258
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• 2016

최근 디스플레이 산업의 발전에 따라 고성능 디스플레이가 요구되며, 디스플레이의 백플레인 (backplane) TFT (thin film transistor) 구동속도를 증가시키기 위한 연구가 활발히 진행되고 있다. 트랜지스터의 구동속도를 증가시키기 위해 높은 이동도는 중요한 요소 중 하나이다. 그러나, 기존 백플레인 TFT에 주로 사용된 amorphous silicon (a-Si)은 대면적화가 용이하며 가격이 저렴하지만, 이동도가 낮다는 (< $1cm2/V{\cdot}s$) 단점이 있다. 따라서 전기적 특성이 우수한 산화물 반도체가 기존의 a-Si의 대체 물질로써 각광받고 있다. 산화물 반도체는 비정질 상태임에도 불구하고 a-Si에 비해 이동도 (> $10cm2/V{\cdot}s$)가 높고, 가시광 영역에서 투명하며 저온에서 공정이 가능하다는 장점이 있다. 하지만, 차세대 디스플레이 백플레인에서는 더 높은 이동도 (> $30cm2/V{\cdot}s$)를 가지는 TFT가 요구된다. 따라서, 본 연구에서는 차세대 디스플레이에서 요구되는 높은 이동도를 갖는 TFT를 제작하기 위하여, amorphous In-Ga-Zn-O (a-IGZO) 채널하부에 화학적으로 안정하고 전도성이 뛰어난 SnO2 채널을 얇게 형성하여 TFT를 제작하였다. 표준 RCA 세정을 통하여 p-type Si 기판을 세정한 후, 열산화 공정을 거쳐서 두께 100 nm의 SiO2 게이트 절연막을 형성하였다. 본 연구에서 제안된 적층된 채널을 형성하기 위하여 5 nm 두계의 SnO2 층을 RF 스퍼터를 이용하여 증착하였으며, 순차적으로 a-IGZO 층을 65 nm의 두께로 증착하였다. 그 후, 소스/드레인 영역은 e-beam evaporator를 이용하여 Ti와 Al을 각각 5 nm와 120 nm의 두께로 증착하였다. 후속 열처리는 퍼니스로 N2 분위기에서 $600^{\circ}C$의 온도로 30 분 동안 실시하였다. 제작된 소자에 대하여 TFT의 전달 및 출력 특성을 비교한 결과, SnO2 층을 형성한 TFT에서 더 뛰어난 전달 및 출력 특성을 나타내었으며 이동도는 $8.7cm2/V{\cdot}s$에서 $70cm2/V{\cdot}s$로 크게 향상되는 것을 확인하였다. 결과적으로, 채널층 하부에 SnO2 층을 형성하는 방법은 추후 높은 이동도를 요구하는 디스플레이 백플레인 TFT 제작에 적용이 가능할 것으로 기대된다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.