• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.53-57
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• 1985

Comparisons and analyses were made of the properties of double or triple passivation layer structures composed of APCVD SiOt or PSG and PECVD SiN films with various layer combinations and layer thicknesses. As a result of the analyses of the pro.peHics such as threshold-voltage shift, crack resistance, pinhole density, and moisture reslstancei a con-clusion was reached that the proper passivation layer structure is the double layer consisting of a 4,00$\AA$ or thicker PSG film and a 6,000$\AA$ SiN film.

• Journal of IKEEE
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• v.20 no.3
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• pp.330-332
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• 2016

In this study, we investigate the influence of channel length of bendable a-Si:H thin film transistors (TFTs) on their electrical characteristics as a function of bending strain. Under a tensile strain of 1.69%, $8{\mu}m$-channel-length TFT has the threshold voltage shift up to 5.25 V, while $100{\mu}m$-channel-length TFT operates stably.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.469-472
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• 1987

The hot-carrier induced degradation in very short-channel MOSFET was studied systematically. Under the traditional DC stress conditions, the threshold voltage shift (${\Delta}Vt$) and the transconductance degradation (${\Delta}Gm$/(Gmo-${\Delta}Gm$)) were confirmed to depend exponentially on the stress time and the dependency between the two parameters was proved to be linear. And the degradation due to the DC stress across gate and drain was studied. As the AC dynamic process is more realistic in actual device operation, the effects of dynamic stresses were studied.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.248-249
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• 2007

본 연구에서는 능동 구동형 유기 발광 소자(AMOLED)에 쓰이는 수소화된 비정질 실리콘(a-Si:H)의 전류 안정성(stability)을 개선하기 위한 새로운 구동방법(driving method)을 제안한다. 제안된 방식은 한 프레임 시간 중 특정 시간동안 비정질 실리콘 박막 트랜지스터(Thin Film Transistor, TFT)에 음의 화상데이터전압을 인가함으로써 열화(degradation)를 억제한다. 비정질 실리콘 박막트랜지스터의 열화를 회복하기 위한 음의 화상데이터의 진폭은 실제 이미지를 표현하는 이전에 인가한 양의 화상데이터에 의해 결정된다. 본 연구에서 제안된 구동방식을 시뮬레이션을 통하여 화소 회로의 동작을 검증하였고, 이를 통해 비정질 실리콘 박막 트랜지스터의 열화가 억제되는 것과 화면의 균일성(screen uniformity) 개선하고자 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.117-117
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• 2007

The physical and electrical properties of nitrided Hf-silicate films, incorporated by NO gas annealing, were investigated by XPS, NEXAFS, TEM and C-V measurement. We confirmed the nitrogen incorporation during NO gas annealing treatment effectively enhances the thermal stability of Hf-silicate. The suppression of phase separation was observed in Hf-silicate films with high nitrogen contents. The negative shift of threshold voltage is caused by the incorporation of nitrogen in the hafnium silicate films.

• Transactions on Electrical and Electronic Materials
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• v.13 no.1
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• pp.47-49
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• 2012

In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.299-299
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• 2011

A dipolar interlayer can cause dramatic changes in the device characteristics of organic field-effect transistors (OFETs) or photovoltaics. A shift in the threshold voltage, for example, has been observed in an OFET where the organic semiconductor active layer is deposited on SiO2 modified with a dipolar monolayer. Dipolar molecules can similarly be used to change the current-voltage characteristics of organic-inorganic heterojunctions. We have conducted a series of experiments in which different molecular linkages are placed between a pentacene thin film and a silicon substrate. Interface modifications with different linkages allow us to predict and examine the nature of tunneling through pentacene on modified Si surfaces with different dipole moment. The molecular-scale structure and the tunneling properties of pentacene thin films on modified Si (001) with nitrobenzene and styrene were examined using scanning tunneling spectroscopy. Electronic interfaces using organic surface dipoles can be used to control the band lineups of a semiconductor at organic/inorganic interfaces. Our results can provide insights into the charge transport characteristics of organic thin films at electronic interfaces.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.154-154
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• 2013

In this work, we investigated the characteristics and the effects of light on the negative gate bias stress stability (NBS) in high mobility polycrystalline IGO TFTs. IGO TFT showed a high drain current on/off ratio of ${\sim}10^9$, a field-effect mobility of $114cm^2/Vs$, a threshold voltage of -4V, and a subthresholdslpe(SS) of 0.28V/decade from log($I_{DS}$) vs $V_{GS}$. IGO TFTs showed large negative $V_{TH}$ shift(17V) at light power of $5mW/cm^2$ with negative gate bias stress of -10V for 10000seconds, at a fixed drain voltage ($V_{DS}$) of 0.5V.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.48-52
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• 1998

We fabricated the newly proposed nano structure memory with SOI edge channel and a nano dot. The width of the edge channel of this device, which uses the side wall as a channel and has a nano dot on this channel region, was determined by the thickness of the recessed top-silicon layer of SOI wafer. The size of side-wall nano dot was determined by the RIE etch and E-Beam lithography. The I$_{d}$-V$_{d}$, I$_{d}$-V$_{g}$ characteristics of the devices without nano dots and memory characteristics of the devices with nano dots were obtained, where the voltage scan was done between -20 V and 14 V and the threshold voltage shift was about 1 V.t 1 V.