• Transactions of the Korean Society of Mechanical Engineers
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• 제14권5호
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• pp.1181-1185
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• 1990

A failure evaluation diagram to evaluate fatigue fracture was developed. The relation between the fatigue limit and the threshold stress intensity factor for the short-cracked specimens of various materials including a piping carbon steel can be rationally predicted by the proposed method. It is shown that the coupled failure evaluation diagram for fatigue and ductile fracture is expecially useful for evaluation of the flaw tolerance as well as the margin of the safety of the pressure vessel and piping. Further, accumulation of fatigue data will be needed to construct an accurate fatigue failure evaluation diagram.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1988년도 한국자동제어학술회의논문집(국내학술편); 한국전력공사연수원, 서울; 21-22 Oct. 1988
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• pp.103-108
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• 1988

A walking robot must have the ability to change the body direction in order to avoid the obstacles. In this paper, we develop a gait control algorithm that can maintain the stable movement of the robot for three different modes of changing directions. The algorithm makes it possible for the robot to have the larger gait stability margin than the threshold value by the method of changing the body speed.

• Journal of Satellite, Information and Communications
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• 제10권3호
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• pp.131-136
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• 2015

In this paper, prior to the flight model X-band dual-mode circular cavity filter required for the high power transmission of the observation payload in the geostationary satellite, the development model are designed and analyzed to show the analytical multipactor requirement margin. First of all, the multipaction breakdown power sensitivities were analyzed by changing the iris width and thickness within the filter, and through that the iris width and thickness was selected and then the multipaction threshold powers over the frequencies within the bandwidth were analyzed and the required margin of 8 dB was obtained. Also for the high power transmission filter, another important phenomena known as corona breakdown are analyzed for the iris width and thickness changes. Finally the development model manufactured was tested and the results met the key requirements.

• Proceedings of the KIEE Conference
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• 대한전기학회 2002년도 하계학술대회 논문집 A
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• pp.229-231
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• 2002

The digital current differential relaying scheme is widely used for primary protection of 765(kV) power transformer. The current differential relay pickup the internal fault at the threshold which is set at 30% of rating current. Margin of 30% include current transformer error 5%, relay error 5%, on load tap changer error 7% and margin factor 140% obtained from the field experience. In this paper transformer protection relay and relay setting rule of high voltage power system are discussed. And we verify the correctness of relay setting rule with current differential relay using Matlab simulation.

• Journal of Advanced Navigation Technology
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• 제23권6호
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• pp.584-588
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• 2019

Wireless body area network (WBAN) is a networking technology that enables early detection of abnormal health conditions, real-time medical monitoring, and telemedicine support systems. The internet of things (IoT) for healthcare, which has become an issue recently, is one of the most promising areas for improving the quality of human life. It must meet the high QoS requirements of the medical communication system like any other communication system. Therefore, the bit error rate (BER) threshold was chosen to accommodate the QoS requirements of the WBAN communication system. In this paper, we calculated BER performance of WBAN channel using IR-UWB PPM modulation and analyzed link budget and system margin of WBAN according to various system parameters.

• Asian Journal of Business Environment
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• 제8권3호
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• pp.23-31
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• 2018

Purpose - The purpose of this study is to analyze the comparative financial performance of outsourcing and vertically integrated corporations from Footwear and Apparel industry. Research design, data, and methodology - Secondary data is collected from the published audited annual reports of the footwear and apparel corporations listed on stock exchanges globally. In the current study, 40 footwear firms have been opted that include 20 vertically integrated and 20 outsourcing firms. The sample is distributed into two groups based on threshold up-to 50 percent respectively outsourcing and vertically integrated companies. Sample independent t-test is applied to compare the financial performance of outsourcing and vertically integrated firms. Results - Based on the investigation of 10 years' data of financial ratio, the results of the study show that there is significant difference between outsourcing and vertical integration strategy on return on assets, return on equity while insignificant difference has found with profit margin. Conclusions - The findings of the current study indicates that there is significant difference between the financial performance of outsourcing and vertically integrated firms in terms of return on asset, return on equity and insignificant difference in terms of profit margin.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.67-75
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• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• Journal of IKEEE
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• 제14권2호
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제32A권11호
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• pp.71-78
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• 1995

Based on the popular 4-transistor SRAM cell, an analytical expression of the minimum cell ratio was derived by modeling the static read operation. By analyzing the relatively simple expression for the minimum cell ratio, which was derived assuming the ideal transistor characteristics, effects of the changes in supply voltage and process parameters on the minimum cell ratio was predicted, and the minimum power supply voltage for read operation was determined. The results were verified by simulations utilizing the suggested simulation method, which is suitable for monitoring the lower limit of supply voltage for proper cell operation. From the analysis, it was shown that the worst condition for cell operation is low temperature and low supply voltage, and that the operation margin can be effectively improved by reducing the threshold voltage of the cell transistors.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.537-542
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• 2014

The three-dimensional (3-D) NAND flash structure with fully charge storage using edge fringing field effect is presented, and its programming characteristic is evaluated. We successfully confirmed that this structure using fringing field effect provides good program characteristics showing sufficient threshold voltage ($V_T$) margin by technology computer-aided design (TCAD) simulation. From the simulation results, we expect that program speed characteristics of proposed structure have competitive compared to other 3D NAND flash structure. Moreover, it is estimated that this structural feature using edge fringing field effect gives better design scalability compared to the conventional 3D NAND flash structures by scaling of the hole size for the vertical channel. As a result, the proposed structure is one of the candidates of Terabit 3D vertical NAND flash cell with lower bit cost and design scalability.