• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.6
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• pp.588-593
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• 2023

The advantage of OTFT technology is that large-area circuits can be manufactured on flexible substrates using a low-cost solution process such as inkjet printing. Compared to silicon-based inorganic semiconductor processes, the process temperature is lower and the process time is shorter, so it can be widely applied to fields that do not require high electron mobility. Materials that have utility as electrode materials include carbon that can be solution-processed, transparent carbon thin films, and metallic nanoparticles, etc. are being studied. Recently, a technology has been developed to facilitate charge injection by coating the surface of the Al electrode with solution-processable titanium oxide (TiOx), which can greatly improve the performance of OTFT. In order to commercialize OTFT technology, an appropriate method is to use a complementary circuit with excellent reliability and stability. For this, insulators and channel semiconductors using organic materials must have stability in the air. In this study, carbon-doped Mo (MoC) thin films were fabricated with different graphite target power densities via unbalanced magnetron sputtering (UBM). The influence of graphite target power density on the structural, surface area, physical, and electrical properties of MoC films was investigated. MoC thin films deposited by the unbalanced magnetron sputtering method exhibited a smooth and uniform surface. However, as the graphite target power density increased, the rms surface roughness of the MoC film increased, and the hardness and elastic modulus of the MoC thin film increased. Additionally, as the graphite target power density increased, the resistivity value of the MoC film increased. In the performance of an organic thin film transistor using a MoC gate electrode, the carrier mobility, threshold voltage, and drain current on/off ratio (I_on/I_off) showed 0.15 cm²/V·s, -5.6 V, and 7.5×10⁴, respectively.

• Journal of the Semiconductor & Display Technology
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• v.9 no.1
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• pp.29-33
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• 2010

Recently, the growth of ZnO thin film on glass substrate has been investigated extensively for transparent thin film transistor. We have studied the phase transition of ZnO thin films from metal to semiconductor by changing RF power in the deposition process by RF magnetron sputtering system. The structural, electric, and optical properties of the ZnO thin films were investigated. The film deposited with 75 watt of RF power showed n-type semiconductor characteristic having suitable resistivity $-3.56\;{\times}\;10^{+1}\;{\Omega}cm$, carrier concentration $-2.8\;{\times}\;10^{17}\;cm^{-3}$, and mobility $-0.613\;cm^2V^{-1}s^{-1}$ while other films by 25, 50, 100 watt of RF power closed to metallic films. From the surface analysis (AFM), the number of crystal grain of ZnO thin film increased as RF power increased. The transmittance of the film was over 88% in the visible region regardless of the change in RF power.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.93-98
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• 2013

In this paper, We have fabricated PMMA thin films by plasma polymerization method for organic thin film transistor's insulator layer. For improving the characteristics of organic transistor, we tested transistor's mobility and output values with organic transistor's electrode structures. As a results, the mobility of top contact was $8{\times}10^{-3}[cm^2V^{-1}s^{-1}]$, that of bottom contact was $2{\times}10^{-4}[cm^2V^{-1}s^{-1}]$. Also, off current of bottom contact was increased. Therefore, we recommend the top contact electrode structure of organic transistor.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.94-97
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• 2008

We have fabricated wet-processed thin-film transistors of unsubstituted pentacene by two kinds of fabrications both solution and dispersion processes. Transistor performances with thin film structures including grain structures in the films by two pro cesses are studied.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.374-377
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• 2009

The characteristics of the deposited thin films of the zinc oxide (ZnO) at different oxygen pressures will be elucidated in this work. The resistivity of ZnO thin films were dominated by the carrier concentration under high oxygen pressure conditions while controlled by the carrier mobility at low oxygen ambiences. In addition, we will show the characteristics of the transparent ZnO based thin film transistor (TFT) fabricated at a full room temperature process with gate dielectric of gadolinium oxide ($Gd_2O_3$) thin films.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.157-158
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• 2000

In this study, to get the larger drain current of the device under the same operation condition as the conventional gate dielectric SiNx thin film transistor devices, we introduced new gate dielectric $Ta_2O_5$ thin film which has high dielectric constant $({\sim}25)$ and good electrical reliabilities. For the application for the TFT device, we fabricated the $Ta_2O_5$ gate dielectric TFT on the low-temperature-transformed polycrystalline silicon thin film using the self-aligned implantation processing technology for source/drain and gate doping. The $Ta_2O_5$ gate dielectric TFT showed better electrical performance than SiNx gate dielectric TFT because of the higher dielectric constant.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1627-1634
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• 2017

In this work, a junctionless transistor with different film thickness of amorphous InGaZnO has been fabricated and it's instability has been analyzed with different film thickness under positive and negative gate stress as well as light illumination. It was found that the threshold voltage shift and the variation of drain current have been increased with decrease of film thickness under the condition of gate stress and light illumination. The reasons for the observed results have been explained by stretched-exponential model and device simulation. Due to the reduced carrier trapping time with decrease of film thickness, electrons and holes can be activated easily. Due to the increase of vertical channel electric field reaching the back interface with decrease of film thickness, more electrons and holes can be accumulated in back interface. When one decides the film thickness for the fabrication of junctionless transistor, the more significant device instability with decrease of film thickness should be consdered.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.2
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• pp.110-118
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• 2002

Organic thin film transitors(OTFT) are of interest for use in broad area electronic applications. And recently organic electroluminescent devices(OELD) have been intensively investigated for using in full-color flat-panel display. We have fabricated inverted-staggered structure OTFTs at lower temperature using the fused-ring polycyclic aromatic hydrocarbon pentacene as the active eletronic material and photoacryl as the organic gate insulator. The field effect mobility is 0.039∼0.17 ㎠/Vs, on-off current ratio is 10$\^$6/, and threshold voltage is -7V. And here we report the study of driving emitting, Ir(ppy)$_3$, phosphorescent OELD with all organic thin film transistor and investigated its electrical characteristics. The OELD with a structure of ITO/TPD/8% Ir(ooy)$_3$ doped in BCP/BCP/Alq$_3$/Li:Al/Al and OTFT with a structure of inverted-stagged Al(gate electrode)/photoacry(gate insulator)/pentacene(p-type organic semiconductor)/ Au(source-drain electrode) were fabricated on the ITP patterned glass substrate. The electrical characteristics are turn-on voltage of -10V, and maximum luminance of about 90 cd/㎡. Device characteristics were quite different with that of only OELD.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.6
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• pp.507-511
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• 2006

We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from $7{\mu}m\;to\;15{\mu}m$. As the polysilicon-2 thickness increased up to $1000\;{\AA}$, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.32.1-32.1
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• 2007