• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.208-208
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• 2013

Graphene has emerged as a fascinating material for next-generation nanoelectronics due to its outstanding electronic properties. In particular, graphene-based field effect transistors (GFETs) have been a promising research subject due to their superior response times, which are due to extremely high electron mobility at room temperature. The biggest challenges in GFET applications are control of carrier concentration and opening the bandgap of graphene. To overcome these problems, three approaches to doping graphene have been developed. Here we demonstrate the decoration of Ni nanoparticles (NPs) on graphene films by simple annealing for p-type doping of graphene. Ni NPs/graphene films were fabricated by coating a $NiCl2{\cdot}6H2O$ solution onto graphene followedby annealing. Scanning electron microscopy and atomic force microscopy revealed that high-density, uniformly sized Ni NPs were formed on the graphene films and the density of the Ni NPs increased gradually with increasing $NiCl2{\cdot}6H2O$ concentration. The formation of Ni NPs on graphene films was explained by heat-driven dechlorination and subsequent particlization, as investigated by X-ray photoelectron spectroscopy. The doping effect of Ni NPs onto graphene films was verified by Raman spectroscopy and electrical transport measurements.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1295-1296
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• 2006

수소화된 비정질 실리콘 박막 트랜지스터(a-Si:H TFT)의 이력 현상이 능동형 유기 발광 다이오드(Active-Matrix Organic Light Emitting Diode) 디스플레이 패널을 구동할 경우에, 발생할 수 있는 잔상(Residual Image) 문제를 단위 소자 및 회로에서 실험을 통하여 규명하였다. 게이트 시작 전압을 바꾸어 VGS-ID 특성을 측정할 경우, 게이트 시작 전압이 5V에서 시작한 VGS-ID 곡선이 10V에서 시작한 VGS-ID 곡선에 비해 왼쪽으로 0.15V 이동하였다. 이러한 결과는 게이트 시작 전압의 차이에 의해 발생한 트랩된 전하량(Trapped Charge) 변화로 설명할 수 있다. 또한, 인가하는 게이트 전압 간격을 0.5V에서 0.05V로 감소시켰을 때 전하 디트래핑 비율의 변화(Charge De-trapping Rate)로 인하여, 이력 현상(Hysteresis Phenomenon)으로 인한 단위 소자에서의 문턱전압의 변화가 0.78V에서 0.39V로 감소함을 관찰하였다. 제작된 2-TFT 1-Capacitor의 ANGLED 화소에서 (n-1)번째 프레임에서의 OLED 전류가 (n)번째 프레임에서의 OLED 전류에 35%의 전류오차를 발생시키는 것을 측정 및 분석하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.473-479
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• 2011

In this paper, we have compared amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) with the nano-crystalline embedded-IGZO ($N_c$-embedded-IGZO) TFT fabricated by solid-phase crystallization (SPC) technique. The field effect mobility (${\mu}_{FE}$) of $N_c$-embedded-IGZO TFT was 2.37 $cm^2/Vs$ and the subthreshold slope (S-factor) was 0.83 V/decade, which showed lower performance than those of a-IGZO TFT (${\mu}_{FE}$ of a-IGZO was 9.67 $cm^2/Vs$ and S-factor was 0.19 V/decade). This results originated from generation of oxygen vacancies in oxide semiconductor and interface between gate insulator and semiconductor due to high temperature annealing process. However, the threshold voltage shift (${\Delta}V_{TH}$) of $N_c$-embedded-IGZO TFT was 0.5 V, which showed 1 V less shift than that of a-IGZO TFT under constant current stress during $10^5$ s. This was because there were additionally less increase of interface trap charges in Nc-embedded-IGZO TFT than a-IGZO TFT.

• Journal of Convergence for Information Technology
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• v.9 no.3
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• pp.75-81
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• 2019

In this work, we investigated a low temperature polycrystalline silicon (LTPS) thin film transistors fabrication process on polymer layers. Dehydrogenation and activation processes were performed by a furnace annealing at a temperature of $430^{\circ}C$ for 2 hr. The crystallization of amorphous silicon films was formed by excimer laser annealing (ELA) method. The p-type device performance, fabricated by polycrystalline silicon (poly-Si) films, shows a very good performance with field effect mobility of $77cm^2/V{\cdot}s$ and on/off ratio current ratio > $10^7$. We believe that the poly-Si formed by a LTPS process may be well suited for fabrication of poly-Si TFTs for bendable panel displays such as AMOLED that require circuit integration.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.87-96
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• 2019

Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.769-772
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• 2014

The device reliability in amorphous InGaZnO under NBS(Negative Bias Stress) and hot carrier stress with different gate overlap has been characterized. Amorphous InGaZnO thin film transistor has been measured. and is channel $width=104{\mu}m$, $length=10{\mu}m$ with gate overlap $length=0,1,2,3{\mu}m$. The device reliability has been analyzed by I-V characteristics. From the experiment results, threshold voltage variation has been increased with increasing of the gate overlap length after hot carrier stress. Also, threshold voltage variation has been decreased and Hump Effect has been observed later with increasing of the gate overlap length after NBS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.137-137
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• 2009

Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.37-42
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• 2006

The preparation and processing of PVP-gate insulators on the device performance have been studied in the fabrication of organic thin film transistors (OTFTs). One of polyvinyl series, poly-4-vinyl phenol(PVP) was used as a solute and propyleneglycol monomethyl etheracetate(PGMEA) as a solvent in the formation of organic gate solutions. The cross-linking of organic insulators was also attempted by adding the thermosetting material, poly (melamine-co-formaldehyde) as a hardener in the compounds. From the measurements of electrical insulating characteristics of metal-insulator-metal (MIM) samples, PVP-based insulating layers showed lower leakage current according to the increase of concentration of PVP and poly (melamine-co-formaldehyde) to PGMEA in the formation of organic solutions. The PVP(20 wt%) copolymer with composition of 20 wt% PVP to PGMEA and cross-linked PVPs in which 5 wt% and 10 wt% poly (melamine-co-formaldehyde) hardeners had been additional]y mixed into PVP(20 wt%) copolymers were used as gate dielectrics in the fabrication of OTFTs, respectively. In our experiments, the maximum field effect mobility of $0.31cm^2/Vs$ could be obtained in the 5 wt% cross-linked PVP(20 wt%) device and the highest on/off current ratio of $1.92{\times}10^5$ in the 10 wt% cross-linked PVP(20 wt%) device.

• Journal of the Semiconductor & Display Technology
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• v.6 no.4
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• pp.69-73
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• 2007

The MIM(metal-insulator-metal) capacitors with the Al/PMMA/ITO/Glass structures were manufactured according to various PMMA concentration of 1, 2, 4, 6, 8 wt%. The lowest leakage current and the largest capacitance were found to be 2.3 pA and 1.2 nF, respectively, for the device with 2 wt% PMMA concentration. The measured capacitance of the devices was almost same values with the calculated one. The optimum film thickness was obtained at the value of 48 nm, showing that the capacitance and leakage current were 1.92 nF, 0.3 pA at 2 wt%, respectively. From this experiment, the PMMA gate insulator films can be applicable to the organic thin film transistors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.19-25
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• 2008

In this study, we fabricated Organic Thin Film Transistors(OTFTs) with $C_{60}$ hole injection layer between organic semiconductor(pentacene) and metal electrode, and we compared the electrical characteristics of OTFTs with/without $C_{60}$. When the $C_{60}$ hole injection layer was introduced, the mobility and the threshold voltage were improved from 0.298 $cm^2/V{\cdot}s$ and -13.3V to 0.452 $cm^2/V{\cdot}s$ and -10.8V, and the contact resistance was also reduced. When the $C_{60}$ is inserted, the hole injection was enhanced because the $C_{60}$ prevent the unwanted chemical reaction between pentacene and Au. Furthermore, we fabricated the OTFTs using Al as their electrodes. When the OTFTs were made by only aluminum electrode, the channel were not mostly made because of the high hole injection barrier between pentacene and aluminum, but when the $C_{60}$ layer with an optimal thickness was applied between aluminum and pentacene, the device performances were obviously enhanced because of the vacuum energy level shift of Al and the consequent decrease of the hole injection barrier which was induced by the interface dipole formation between $C_{60}$ and Al. The mobility and $I_{ON}/I_{OFF}$ current ratio of OTFT with $C_{60}/Al$ electrode were 0.165 $cm^2/V{\cdot}s$ and $1.4{\times}10^4$ which were comparable with the normal Au electrode OTFT.