• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.220-221
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• 2008

With recent advanced in portable electric devices, wireless sensor, MEMS and bio-Mechanics device, the new typed power supply, not conventional battery but self-powered energy source is needed. Particularly, the system that harvests from their environments are interests for use in self powered devices. For very low powered devices, environmental energy may be enough to use power source. Therefore, in other to made piezoelectric energy harvesting device. The made 31 type triple-morph cantilever was resulted from the conditions of 100k$\Omega$, 0.25g, 154Hz respectively. The thick film was prepared at the condition of $6.57V_{rms}$, and its power was $432.31{\mu}W$ and its thickness was $50{\mu}m$.

• Journal of the Korean institute of surface engineering
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• v.53 no.5
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• pp.257-264
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• 2020

Anodization of Fe and Fe alloys is one of the most promising techniques to obtain iron oxide films applying to the various electrochemical devices due to their electrochemical catalytic properties. In this study, we investigate on the preparation of anodic iron oxide composite incorporated with WO₃ through a single-step anodization of stainless steel type-304 (STS304) as a substrate. The effects of applied voltage and tungsten precursor on the structural characteristics of iron oxide composite with different amount of incorporated WO₃ were observed. It is demonstrated that when the voltage of 60 V applied with 20 mM of Na₂WO₄ as a precursor, anodic iron oxide composite with a large pore diameter and a thick oxide length in which WO₃ is uniformly incorporated is obtained.

• Korean Journal of Materials Research
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• v.18 no.7
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• pp.379-383
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• 2008

We report on the light-emitting diode (LED) characteristics of core-shell CdSe/ZnS nanocrystal quantum dots (QDs) embedded in $TiO_2$thin films on a Si substrate. A simple p-n junction could be formed when nanocrystal QDs on a p-type Si substrate were embedded in ${\sim}5\;nm$ thick $TiO_2$ thin film, which is inherently an n-type semiconductor. The $TiO_2$ thin film was deposited over QDs at $200^{\circ}C$ using plasma-enhanced metallorganic chemical vapor deposition. The LED structure of $TiO_2$/QDs/Si showed typical p-n diode currentvoltage and electroluminescence characteristics. The colloidal core-shell CdSe/ZnS QDs were synthesized via pyrolysis in the range of $220-280^{\circ}C$. Pyrolysis conditions were optimized through systematic studies as functions of synthesis temperature, reaction time, and surfactant amount.

• Transactions on Electrical and Electronic Materials
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• v.8 no.3
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• pp.110-114
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• 2007

Dependence of the thermal stability of nickel silicide on the film stress of inter layer dielectric (ILD) layer has been investigated in this study and silicon nitride $(Si_3N_4)$ layer is used as an ILD layer. Nickel silicide was formed with a one-step rapid thermal process at $500^{\circ}C$ for 30 sec. $2000{\AA}$ thick $Si_3N_4$ layer was deposited using plasma enhanced chemical vapor deposition after the formation of Ni silicide and its stress was split from compressive stress to tensile stress by controlling the power of power sources. Stress level of each stress type was also split for thorough analysis. It is found that the thermal stability of nickel silicide strongly depends on the stress type as well as the stress level induced by the $Si_3N_4$ layer. In the case of high compressive stress, silicide agglomeration and its phase transformation from the low-resistivity nickel mono-silicide to the high-resistivity nickel di-silicide are retarded, and hence the thermal stability is obviously improved a lot. However, in the case of high tensile stress, the thermal stability shows the worst case among the stressed cases.

• Journal of the Korean Ceramic Society
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• v.39 no.4
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• pp.377-385
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• 2002

The possibility of $ZrO_2$ thin film as insulator for Metal-Ferroelectric-Insulator-Semiconductor(MFIS) structure was investgated. $SrBi_2Ta_2O_9$ and $SrBi_2Ta_2O_9$(SBT) thin films were deposited on P-type Si(111) wafer by R. F. magnetron sputtering method. The electrical properties of MFIS gate were relatively improved by inserting the $ZrO_2$ buffer layer. The window memory increased from 0.5 to 2.2V in the applied gate voltage range of 3-9V when the thickness of SBT film increased from 160 to 220nm with 20nm thick $ZrO_2$. The maximum value of window memory is 2.2V in Pt/SBT(160nm)/$ZrO_2$(20nm)/Si structure with the optimum thickness of $ZrO_2$. These memory windows are sufficient for practical application of NDRO-FRAM operating at low voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.77-77
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• 1998

Present silicon dioxide (SiOz) 떠m as intennetal dielectridIMD) layers will result in high parasitic c capacitance and crosstalk interference in 비gh density devices. Low dielectric materials such as f f1uorina뼈 silicon oxide(SiOF) and f1uoropolymer IMD layers have been tried to s이ve this problem. I In the SiOF ftlm, as fluorine concentration increases the dielectric constant of t뼈 film decreases but i it becomes unstable and wa않r absorptivity increases. The dielectric constant above 3.0 is obtain어 i in these ftlms. Fluoropolymers such as polyte$\sigma$따luoroethylene(PTFE) are known as low dielectric c constant (>2.0) materials. However, their $\alpha$)Or thermal stability and low adhesive fa$\pi$e have h hindered 야1리ru뚱 as IMD ma따"ials. 1 The concept of a plasma processing a찌Jaratus with 비gh density plasma at low pressure has r received much attention for deposition because films made in these plasma reactors have many a advantages such as go여 film quality and gap filling profile. High ion flux with low ion energy in m the high density plasma make the low contamination and go어 $\sigma$'Oss피lked ftlm. Especially the h helicon plasma reactor have attractive features for ftlm deposition 야~au똥 of i앙 high density plasma p production compared with other conventional type plasma soun:es. I In this pa야Jr, we present the results on the low dielectric constant fluorocarbonated-SiOF film d밑JOsited on p-Si(loo) 5 inch silicon substrates with 00% of 0dFTES gas mixture and 20% of Ar g gas in a helicon plasma reactor. High density 띠asma is generated in the conventional helicon p plasma soun:e with Nagoya type ill antenna, 5-15 MHz and 1 kW RF power, 700 Gauss of m magnetic field, and 1.5 mTorr of pressure. The electron density and temperature of the 0dFTES d discharge are measUI벼 by Langmuir probe. The relative density of radicals are measured by optic허 e emission spe따'Oscopy(OES). Chemical bonding structure 3I피 atomic concentration 따'C characterized u using fourier transform infrared(FTIR) s야3띠"Oscopy and X -ray photonelectron spl:’따'Oscopy (XPS). D Dielectric constant is measured using a metal insulator semiconductor (MIS;AVO.4 $\mu$ m thick f fIlmlp-SD s$\sigma$ucture. A chemical stoichiome$\sigma$y of 야Ie fluorocarbina$textsc{k}$영-SiOF film 따~si야영 at room temperature, which t the flow rate of Oz and FTES gas is Isccm and 6sccm, res야~tvely, is form려 야Ie SiouFo.36Co.14. A d dielec$\sigma$ic constant of this fIlm is 2.8, but the s$\alpha$'!Cimen at annealed 5OOt: is obtain려 3.24, and the s stepcoverage in the 0.4 $\mu$ m and 0.5 $\mu$ m pattern 킹'C above 92% and 91% without void, res야~tively. res야~tively.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.39-46
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• 2017

This paper presents the fabrication of ceramic insulation layer on metallic heat spreading substrate, i.e. an insulated metal substrate, for planar type heater. Aluminum alloy substrate is preferred as a heat spreading panel due to its high thermal conductivity, machinability and the light weight for the planar type heater which is used at the thermal treatment process of semiconductor device and display component manufacturing. An insulating layer made of ceramic dielectric film that is stable at high temperature has to be coated on the metallic substrate to form a heating element circuit. Two technical issues are raised at the forming of ceramic insulation layer on the metallic substrate; one is delamination and crack between metal and ceramic interface due to their large differences in thermal expansion coefficient, and the other is electrical breakdown due to intrinsic weakness in dielectric or structural defects. In this work, to overcome those problem, selected metal oxide buffer layers were introduced between metal and ceramic layer for mechanical matching, enhancing the adhesion strength, and multi-coating method was applied to improve the film quality and the dielectric breakdown property.

• Proceedings of the Materials Research Society of Korea Conference
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• 1992.05b
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• pp.26-27
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• 1992

The effect of activation and electroless nickel plating conditions on contact properties were investigated for selective electroless nickel plating of Si farers in order to obtain an optimum condition of contact hole filling. According to RCA prosess, p-type si 1 icon (100) surface was cleaned out and activated. The effects of temperture, DMAB concentration, time, and stirring iwere investigated for activation of p-type Si(100) surface. The optimal activation condition obtained was 0.5M HF, 1mM PdCl$_2$, 2mM EDTA, 7$0^{\circ}C$, 90sec under ultrasonic vibration. In electroless nickel plating, the effect of temperature, DMAB concentration, pH, and plating ti me were studied. The optimal plating condition found was 0. 10M NiS0$_4$.$H_2O$, 0.lIM Citrate, pH 6.8, 6$0^{\circ}C$, 30 minutes. The contact resistence of fi]ms wascomparatively low. It took 30 minutes to obtain 1$\mu$m thick film with 8$\mu$M DMAB concentration. The film surface roughness was improved with increasing temperature and decreasing pH of the plating solution. The best quality of the film was obtained with the condition of temperature 6$0^{\circ}C$ and pH 6.8. The micro-victors hardness of film was about 600Hv and was decreased wi th increasing particle size of plating layer.