• 제목/요약/키워드: Test circuit

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Applying Parallel Processing Technique in Parallel Circuit Testing Application for improve Circuit Test Ability in Circuit manufacturing

  • Prabhavat, Sittiporn;Nilagupta, Pradondet
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2005년도 ICCAS
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    • pp.792-793
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    • 2005
  • Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

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Design of Connectivity Test Circuit for a Direct Printing Image Drum

  • Jung, Seung-Min
    • Journal of information and communication convergence engineering
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    • 제6권1호
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    • pp.43-46
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    • 2008
  • This paper proposes an advanced test circuit for detecting the connectivity between a drum ring of laser printer and PCB. The detection circuit of charge sharing is proposed, which minimizes the influences of internal parasitic capacitances. The test circuit is composed of precharge circuit, analog comparator, level shifter. Its functional operation is verified using $0.6{\mu}m$ 3.3V/40V CMOS process parameter by HSPICE. Access time is100ns. Layout of the drum contact test circuit is $465{\mu}m\;{\times}\;117{\mu}m$.

Three-phase Making Test Method for Common Type Circuit Breaker

  • Ryu, Jung-Hyeon;Choi, Ike-Sun;Kim, Kern-Joong
    • Journal of Electrical Engineering and Technology
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    • 제7권5호
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    • pp.778-783
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    • 2012
  • The synthetic short-circuit making test to adequately stress the circuit breaker has been specified as the mandatory test duty in the IEC 62271-100. The purpose of this test is to give the maximum pre-arcing energy during making operation. And this requires the making operation with symmetrical short-circuit current that is established when the breakdown between contact gap occurs near the crest of the applied voltage. Also, if the interrupting chamber of circuit breakers is designed as the type of common enclosure or the operation is made by the gang operated mechanism that three-phase contacts are operated by one common mechanism, three-phase synthetic making test is basically required. Therefore, several testing laboratories have developed and proposed their own test circuits to properly evaluate the breaker performance. With these technical backgrounds, we have developed the new alternative three-phase making circuit.

Weil-Dobke 합성단락시험로의 최적화 연구 (A Study on Optimization of the Weil-Dobkes Synthetic Short-Circuit Tests)

  • 김맹현;고희석
    • 대한전기학회논문지:전력기술부문A
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    • 제50권6호
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    • pp.287-292
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    • 2001
  • This paper deals with the configuration, operating principles, systematic calculation method of parameter and optimization method of test circuit for parallel current injection method, series voltage injection method and hybrid synthetic test method as the method for performance test of circuit breaker with extra high interrupting capacity. The test method depicted above is applied to short-circuit making and breaking test (operating sequence :Os CdOs, Od-CdOs) and out-of-phase tests(operating sequence :Os, CdOs) for performance test of the newly-developed 420kV, 50kA and 800kV 50kV puffer-type gas circuit-breaker according to IEC 60056 and IEC 60427. The testing results, evaluation of equivalence for test and analyzed results are also presented in this paper.

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단락시험에서 후비보호차단기와 투입스위치의 중요 역할 (The study of a primary role of Back up Breaker and Making Switch for Short Circuit Test)

  • 김선구;김선호;김원만;노창일;이동준;정흥수
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 제38회 하계학술대회
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    • pp.915-916
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    • 2007
  • There are many equipments for the Short Circuit Test, for example Short Circuit Generator, Induction Motor, Sequence Timer, Exciter, CLR, Back Up Breaker, Making Switch and TRV etc. Especially Back up Breaker and Making Switch are very important equipments to test the short circuit test. A role of a Back up Breaker is to break high-voltage and high-current for short circuit test and a Making Switch should be operated always same speed/time and kept electrical-mechanical characteristics to make the voltage and current of short circuit test. This study introduces to the short circuit test also to kinds, principal movements and compare them of Back up Breaker and Making Switch.

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Sliding diagonal Pattern에 의한 Memory Test circuit 설계 (Design of Memory Test Circuit for Sliding Diagonal Patterns)

  • 김대환;설병수;김대용;유영갑
    • 전자공학회논문지A
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    • 제30A권1호
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    • pp.8-15
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    • 1993
  • A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

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KERI 합성투입시험회로의 해석적 고찰 (Analytical Examination of KERI Synthetic Short-circuit Current Making Test Circuit)

  • 이용한
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 하계학술대회 논문집 A
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    • pp.455-457
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    • 2003
  • In the present IEC 60427(2000), reduced applied voltage can be used for synthetic short-circuit making current tests if the maximum pre-arcing time of the test circuit breaker is less than $1/{\omega}$. But in the near future IEC, only the making tests with full test voltage shall be allowed. To meet this trend, KERI is preparing synthetic making test facilities using step-up transformer, ITMC and plasma making switch. This paper presents analytical characteristics of KERI's synthetic short-circuit making test circuits. The results of this paper can be useful for effective and adequate tests.

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단락발전기 용 여자장치의 조작과 기능에 대한 고찰 (The study for function and operation of the excitation equipment for short circuit generator)

  • 김선구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.735-736
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    • 2008
  • There are many equipments for the Short Circuit Test, for example Short Circuit Generator, Induction Motor, Sequence Timer, CLR, Back Up Breaker, Making Switch and Excitation Equipment etc. Gradually an allowable tolerance of the short circuit test voltage is become smaller by the standards for short circuit test. The excitation equipment of short circuit generator is very important for test voltage is adjusted by the excitation equipment. Especially the excitation equipment must be possessed character of exactitude, durability and inalterability because some times around 10,000 times opening and closing short circuit test is requested by clint, which must be done within one minute. The purpose of this study for function and operation of the excitation equipment which rated DC voltage is 1,000V, rated DC current is 300A, rated out put is 30kW and type is YNEX 97S-441/609, is to help operation of short circuit generator.

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가속 열화 시험에 따른 저압용 차단기의 물리적 특성에 관한 연구 (A Study on the Physical Characteristics of the Low-voltage Circuit Breaker Based on the Accelerated Degradation Test)

  • 강신동;김재호
    • 한국안전학회지
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    • 제37권6호
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    • pp.1-8
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    • 2022
  • This study analyzed the characteristics of insulation resistance and operating time based on an accelerated degradation test of a low-voltage circuit breaker. The experimental sample used a molded case circuit breaker (MCCB) and an earth leakage circuit breaker (ELCB). After measuring the insulation resistance of the circuit breakers, the leakage current was affected by an external rather than an internal structure. Furthermore, the insulation resistance of the circuit breakers with accelerated degradation was measured using a Megger insulation tester. In the accelerated degradation test, aging times of five, ten, 15, and 20 years were applied according to a temperature derived using the Arrhenius equation. Circuit breakers with an equivalent life of ten, 15, and 20 years had increased insulation resistance compared to those with less degradation time. In particular, the circuit breaker with an equivalent life of ten years had the highest insulation resistance. Component analysis of the circuit breaker manufactured through an accelerated degradation test confirmed that the timing of the increase in insulation resistance and the time of additive loss were the same. Finally, after analyzing the operating time of the circuit breakers with degradation, it was confirmed that the MCCB did not change, but the ELCB breaker failed.

디스플레이 테스트를 위한 패턴 생성 회로 설계 (Design of Pattern Generation Circuit for Display Test)

  • 조경연
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.1149-1152
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    • 2003
  • Now a days, many different kinds of display technologies such as Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED), and Liquid Crystal On Silicon (LCOS) are designed. And these display technologies will be used in many application products like High Definition Televisions (HDTVs) or mobile devices. In this paper, pattern generation circuit for display test is proposed. The proposed circuit will be embedded in the control circuit of display chip. Two differenct kinds of patterns is generated by the circuit. One is block pattern for color test, and the other is line pattern for pixel test. The shape of test pattern is determined by the values of registers in pattern generation circuit. The circuit is designed using Verilog HDL RTL code.

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