• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.18-24
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• 2011

A new problem happens with the evolution of TSV based 3D IC design. The bonding process takes place which follows with the testing of design for proper connectivity in the absence of TSV redundancy. In order to achieve good yield, the design should be tested with redundancy TSV. This paper presents a wrapper cell design for redundancy TSV interconnect test. The design for test technique, in terms of hardware and software perspectives is described. The wrapper cell with hardware design can use original test patterns. However, software design has less area overhead.

• Journal of Biosystems Engineering
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• v.27 no.1
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• pp.11-18
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• 2002

One of the major obstructing factors against managing dairy farm in Korea has been a shortage of roughage supply, which resulted in excessive abuse of concentrate feed. In order to solve this problem, production of the wrap silage by the winter cereal forages raised in the fallow paddy field is strongly recommended in Korea. The main objective is to develop a tractor attached round bale wrapper which can process the silage by wrapping the round bales with thin plastic films. This is the first half of the study which is divided by two parts. In this first part, bale wrapping process was analyzed, and based on this results the followings were designed, developed and tested. 1. Bale wrapper which haying the maximum capacity of 1 ton bale with various functions such as loading, wrapping, discharging the round bales and supplying and cutting wrap films was designed. 2. An actuator and its hydraulic circuit of each process were developed and tested. 3. Also, the variations of hydraulic pressure and engine speed were investigated by operating bale wrapper developed. In this test, maximum pressure of the hydraulic circuit for the bale wrapping was 130 kg/㎠ when it raised the bale, which was quite below the relief pressure of 170 kg/㎠ of hydraulic circuit. In the engine speed test, speed drop was 20∼67 rpm, which meant that there was no over-load operation. Therefore, the experiment proved that developed hydraulic circuit and mechanism is stable in bale wrapping operation

• Aerospace Engineering and Technology
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• v.8 no.2
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• pp.41-53
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• 2009

This study describes to design the interface between VDL (VHF Digital Link) Mode 2 system and AOA (ACARS Over AVLC) network. KARI-Wrapper using aircraft and ground station design requirements should be designed to the system configuration of the in-out interface of the components and analyzed with the ARINC 618, 620, 622 documentations. According to the system interface test, we are verified the satisfactions of uplink and downlink VDL Mode 2 requirements.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.131-136
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• 2013

TSV based 3D ICs have been widely developed with new problems at die and IC levels. It is imperative to test at post-bond as well as pre-bond to achieve high reliability and yield. This paper introduces a new testable design technique which not only test microscopic defects at TSV input/output contact at a die but also test interconnect defects at a stacked IC. IEEE 1500 wrapper cells are augmented and through at-speed tests for pre-bond die and post-bond IC, known-good-die and defect free 3D IC can be massively manufactured+.

• Journal of KIISE:Software and Applications
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• v.31 no.4
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• pp.447-456
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• 2004

Information extraction is a process of recognizing and fetching particular information fragments from a document. In order to extract information uniformly from many heterogeneous information sources, it is necessary to produce information extraction rules called a wrapper for each source. Previous methods of information extraction can be categorized into manual wrapper generation and automatic wrapper generation. In the manual method, since the wrapper is manually generated by a human expert who analyzes documents and writes rules, the precision of the wrapper is very high whereas it reveals problems in scalability and efficiency In the automatic method, the agent program analyzes a set of example documents and produces a wrapper through learning. Although it is very scalable, this method has difficulty in generating correct rules per se, and also the generated rules are sometimes unreliable. This paper tries to combine both manual and automatic methods by proposing a new method of learning information extraction rules. We adopt the scheme of supervised learning in which a user-interface agent is designed to get information from the user regarding what to extract from a document, and eventually XML-based information extraction rules are generated through learning according to these inputs. The interface agent is used not only to generate new extraction rules but also to modify and extend existing ones to enhance the precision and the recall measures of the extraction system. We have done a series of experiments to test the system, and the results are very promising. We hope that our system can be applied to practical systems such as information-mediator agents.

• Korean Journal of Agricultural Science
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• v.47 no.1
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• pp.43-58
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• 2020

Mulching plastic is used for the purpose of maintaining soil temperature, moisture, and weed and pest prevention in agriculture. Any remaining plastic after use may contaminate the soil and damage crop growth. To solve this problem, mulching plastic wrappers have been studied and developed, but the actual use rate is quite low due to their poor performance and frequent tearing of the plastic on the field. In this study, we developed a tractor attachable mulching plastic wrapper to minimize the tearing of the mulched plastic. The developed mulching plastic wrapper consists of hydraulic motors and pumps, valves, a microcontroller, and sensors. The collecting speed of the plastic mulch was calculated considering the tractor's travel speed and the radius of the collecting drum. A proportional controller was designed to control the rotating speed of the hydraulic motor as the plastic was wound around the collection drum and the radius increased. The performance of an indoor experiment was quite promising because the difference between the collecting speed predicted by the calculation and the actual collecting speed was 2.71 rpm. Based on a field verification test, the speed difference was max. 14.28 rpm; thus, the, proportional integral derivative (PID) controller needs to be considered to control the drum speed precisely. Another issue was found when the soil covered at the edge of the plastic was hardened or the road surface was uneven, the speed control was unstable, and the plastic was torn. In future research, vibrational plows will be equipped to break-up the harden soil for collecting the plastic smoothly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.65-73
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• 2007

This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.97-106
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• 2004

A new test strategy for embedded SOC test is proposed. The SOC test is evaluated by the degree that is the amount of the total reduced test time. Since the test time for a embedded core is determined by the configuration of test wrapper, the total test time is decided by the length of the largest TAM used by the test wrapper. So the DFT(Design for Test) must be involved in the design flow. And the efficient test strategy must be settled. The all Previous test strategies are the methods that find a sub-optimal configurations of scan-chains to minimize the test time after the total TAM lines are divided into a few groups. But this is the NP-complete problem so that all attempts which examine such a TAM configuration and scan-chain division are impossible. In this thesis, a new methodology for this problem is proposed and the efficiency of the methodology is proved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.74-79
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• 2006

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.71-81
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• 2008

In this paper, we propose a novel Globally Asynchronous, Locally Dynamic System(GALDS) bus and demonstrate its performance. The proposed GALDS bus is the bidirectional multitasking bus with the segmented bus architecture supporting the concurrent operation of multi-masters and multi-slaves. By analyzing system tasks, the bus architecture chooses the optimal frequency for each If among multiples of bus frequency and thus we can reduce the overall power consumption. For efficient data communications between IPs operating in different frequencies, we designed an asynchronous and bidirectional FIFO based on an asynchronous wrapper with hand-shaking interface. In addition, since systems can be easily expandable by inserting bus segments, the proposed architecture has advantages in IP reusability and structural flexibility As a test example, a four-segment bus haying four masters and four slaves were designed by using Verilog HDL. We demonstrate multitasking operations with read/write data transfers by simulation when the ratios of operation frequency are 1:1, 1:2, 1:4 and 1:8. The data transfer mode is a 16 burst increment mode compatible with Advanced Microcontroller Bus Architecture(AMBA). The maximum operation latency of the proposed GALDS bus is 22 clock cycles for the bus write operation, and 44 clock cycles for read.