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A New Test Technique of SOC Test Based on Embedded Cores for Reducing SOC Test Time  

강길영 (삼성전자 반도체총괄 메모리사업부)
김근배 (연세대학교 전기전자공학과)
임정빈 (연세대학교 전기전자공학과)
전성훈 (연세대학교 전기전자공학과)
강성호 (연세대학교 전기전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.9, 2004 , pp. 97-106 More about this Journal
Abstract
A new test strategy for embedded SOC test is proposed. The SOC test is evaluated by the degree that is the amount of the total reduced test time. Since the test time for a embedded core is determined by the configuration of test wrapper, the total test time is decided by the length of the largest TAM used by the test wrapper. So the DFT(Design for Test) must be involved in the design flow. And the efficient test strategy must be settled. The all Previous test strategies are the methods that find a sub-optimal configurations of scan-chains to minimize the test time after the total TAM lines are divided into a few groups. But this is the NP-complete problem so that all attempts which examine such a TAM configuration and scan-chain division are impossible. In this thesis, a new methodology for this problem is proposed and the efficiency of the methodology is proved.
Keywords
SOC 테스트;스케줄링 TAM;
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