• Journal of IKEEE
• /
• v.8 no.1 s.14
• /
• pp.47-53
• /
• 2004

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• 전기의세계
• /
• v.28 no.1
• /
• pp.43-52
• /
• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.10
• /
• pp.52-62
• /
• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.347-350
• /
• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• Journal of Sensor Science and Technology
• /
• v.33 no.3
• /
• pp.134-138
• /
• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.3
• /
• pp.491-499
• /
• 2007

In this paper, we present a design method of the ternary logic circuits based on Reed-Muller expansions. The design method of the presented ternary logic circuits checks the degree of each variable for the coefficients of Reed-Holler Expansions(RME) and determines the order of optimal control input variables that minimize the number of Reed-Muller Expansions modules. The order of optimal control input variables is utilized the computation of circuit cost matrix. The ternary logic circuits of the minimized tree structures to be constructed by RME modules based on Reed-Muller Expansions are realized using the computation results of its circuit cost matrix. This method is only performed under unit time in order to search for the optimal control input variables. Also, this method is able to be programmed by computer and the run time on programming is $3^n$.

• Journal of Sensor Science and Technology
• /
• v.33 no.3
• /
• pp.152-157
• /
• 2024

In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of V_DD/2 and V_DD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when V_DD is set to 0.9 V.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.12
• /
• pp.1552-1564
• /
• 1995

A fault detecting method of ternary logic is proposed by using the spectral coefficients of the Chrestenson function. Fault detecting conditions are derived for a stuck-at fault in case of single input, multiple inputs and internal lines in the ternary logic. The detecting conditions for min/max bridging faults are also considered. When using this fault analysis method, it is possible to detect faults without the test vector and minimize high volume memory for storing the vector and response data. Thus, the computational complexity for the test vector can be decreased.

• Journal of Applied and Pure Mathematics
• /
• v.6 no.1_2
• /
• pp.97-103
• /
• 2024

This study is about digits of numbers in system logic B₃. Any real number is written as digits in the binary system, in the ternary system. The numbers in base two and base three are also written in the B₃ system ternary logic. These two writing methods are transferred into the third method. The real numbers 0,1 and 0, 1, 2 are written as digits. The same real numbers are written as digits of elements of the set -1, 0, 1 in base B₃. The periods here are investigated. The relationship between these digits is analysed.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.1
• /
• pp.57-63
• /
• 1994

The logic function synthesis using ULM U$_h$ is constructed based on canonic Reed-Muller expansion coefficient for a given function. This paper proposes the fast synthesis algorithm using ULM U$_h$ for ternary function. By using circuit cost and synthesis method of proposed in this paper, order of control input variable minimum number of ULM U$_h$ can be decided in the synthesis of n-variable ternary function. Accordingly, this method enables to optimum circuit realization for ternary function synthesis using ULM ULM U$_h$ and can be applied to ternary function synthesis using ULM U$_h$. The complexity of search for select the order of all control input variables is (n+2)(n-1)/2.