• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1716-1725
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• 1996

In this paper, the huffman decoder which is a part of the decoder in JPEG standard format is designed by using a new Ternary CAM. First, the 256 word * 16 bit-size new bit-word all parallel Ternary CAM system is designed and verified using SPICE and CADENCE Verilog-XL, and then the verified novel Ternary CAM is applied to the new huffman decoder architecture of JPEG. So the performnce of the designed CAM cell and it's block is verified. The new Ternary CAM has various applications because it has search data mask and storing data mask function, which enable bit-wise search and don't care state storing. When the CAM is used for huffman look-up table in huffman decoder, the CAM is partitioned according to the decoding symbol frequency. The scheme of partitioning CAM for huffman table overcomes the drawbacks of all-parallel CAM with much power and load. So operation speed and power consumption are improved.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1535-1538
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• 2002

The flexibility of content addressable mem-ory (CAM) can greatly be extended through the use of trits (ternary digits) Trits consist of binary logical values “0” and “1” with addition of “x” (“dont’t care”). The “dont’t care“is extremely useful for providing com- pact representation of sets of bit strings. In this paper, we propose a new ternary CAM with Hamming distance search functions. Each memory cell in the CAM consists of a pair of lambda diodes which can store trits, namely, a logical “0”, “1” and “x” (“dont’t care“). The CAM can compare stored data and an input data in parallel, and find stored data with Hamming distance within a certain range (“near match“). Also, the interrogation characteristics of the ternary CAM are analyzed in detail. Furthermore, the results obtained these analyses are fully confirmed by simulation using the circuit analysis program HSPICE.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.458-464
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• 2017

A magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM) is proposed which provides non-volatility. A unit cell of the TCAM has two MTJ's and 4.875 transistors, which allows the realization of TCAM in a small area. The equivalent resistance of parallel connected multiple unit cells is compared with the equivalent resistance of parallel connected multiple reference resistance, which provides the averaging effect of the variations of device characteristics. This averaging effect renders the proposed TCAM to be variation-tolerant. Using 65-nm CMOS model parameters, the operation of the proposed TCAM has been evaluated including the Monte-Carlo simulated variations of the device characteristics, the supply voltage variation, and the temperature variation. With the tunneling magnetoresistance ratio (TMR) of 1.5 and all the variations being included, the error probability of the search operation is found to be smaller than 0.033-%.

• International Journal of CAD/CAM
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• v.5 no.1
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• pp.29-38
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• 2005

A non-uniform 3-point ternary interpolatory subdivision scheme with variable subdivision weights is introduced. Its support is computed. The $C^0$ and $C^1$ convergence analysis are presented. To elevate its controllability, a modified edition is proposed. For every initial control point on the initial control polygon a shape weight is introduced. These weights can be used to control the shape of the corresponding subdivision curve easily and purposefully. The role of the initial shape weight is analyzed theoretically. The application of the presented schemes in designing smooth interpolatory curves and surfaces is discussed. In contrast to most conventional interpolatory subdivision scheme, the presented subdivision schemes have better locality. They can be used to generate $C^0$ or $C^1$ interpolatory subdivision curves or surfaces and control their shapes wholly or locally.

• International Journal of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.121-138
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• 2024

Artificial intelligence is crucial to manufacturing productivity. Understanding the difficulties in producing disruptions, especially in linear feed robot systems, is essential for efficient operations. These mechanical tools, essential for linear movements within systems, are prone to damage and degradation, especially in the LM guide, due to repetitive motions. We examine how explainable artificial intelligence (XAI) may diagnose wafer linear robot linear rail clearance and ball screw clearance anomalies. XAI helps diagnose problems and explain anomalies, enriching management and operational strategies. By interpreting the reasons for anomaly detection through visualizations such as Class Activation Maps (CAMs) using technologies like Grad-CAM, FG-CAM, and FFT-CAM, and comparing 1D-CNN with 2D-CNN, we illustrates the potential of XAI in enhancing diagnostic accuracy. The use of datasets from accelerometer and torque sensors in our experiments validates the high accuracy of the proposed method in binary and ternary classifications. This study exemplifies how XAI can elucidate deep learning models trained on industrial signals, offering a practical approach to understanding and applying AI in maintaining the integrity of critical components such as LM guides in linear feed robots.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10c
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• pp.575-580
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• 2006

인터넷 네트워크에 존재하는 방화벽(Firewall) 또는 라우터(Router) 장비에서의 패킷 필터 기능은 모든 방화벽 장비의 기본적인 기능이 될 수 있다. 하지만 최근에 등장한 세션기반의 악의적 침입과 바이러스의 출현으로 패킷 필터기는 단순한 정적 패킷 필터 기능이 아닌 상태기반 패킷 필터의 동적 패킷 필터 기능을 요구하게 되었다. 또한 최근에 인터넷 속도가 급증하는 환경변화에 맞추어 방화벽 장비의 TCP 패킷 처리기능은 매우 빠른 처리속도를 요구하고 있다. 이에 우리는 매우 빠른 고속의 TCP 상태기반 패킷 필터 처리를 요구하는 에지(Edge)급 라우터의 방화벽 옵션카드를 만들기 위해 하드웨어 기반의 TCAM(Ternary CAM) 관리를 이용한 TCP 세션 상태기반 (Stateful) 패킷 필터기를 구현하였으며, TCAM 제어와 패킷의 상태기반 검사 등 모든 기능처리는 FPGA(Field Programmable Gate Array)를 이용한 하드웨어 로직(Logic) 및 상태기(State Machine)로 구현하였다. 그리고 본 논문의 구현방식을 적용한 방화벽 옵션카드는 인-라인(In-line) 모드로 구성될 경우 1GHz 이상의 Wire Speed를 만족하는 처리성능을 보여주었다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.1
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• pp.88-95
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• 2009

This paper presents a traffic pattern matching hardware that can be used in high performance network applications. The presented hardware is designed for a contents security system which is to block various kinds of information drain or intrusion activities. The hardware consists of two parts: the header lookup and string pattern matching parts. For implementing the header lookup part in hardware, the TCAMs(ternary CAMs) are popularly used. Since the TCAM approach is inefficient in terms of the hardware and memory costs and the power consumption, however, we adopt and modify an alternative approach based on the comparator arrays and the HiCuts tree. Our implementation results, using Xilinx FPGA XC4VSX55, show that our design can reduce the usage of the FPGA slices by about 26%, and the Block RAM by about 58%. In the design of string pattern matching part, we design and use a hashing module based on cellular automata, which is hardware efficient and consumes less power by adaptively changing its configuration to reduce the collision rates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.345-353
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• 2003

When designing network processors or implementing network equipments such as routers are implemented, IP lookup operations cause the major impact on their performance. As the organization of the IP address becomes simpler, the speed of the IP lookup operations can go faster. However, since the efficient management of IP address is inevitable due to the increasing number of network users, the address organization should become more complex. Therefore, for both IPv4(IP version 4) and IPv6(IP version 6), it is the essential fact that IP lookup operations are difficult and tedious. Lots of researcher for improving the performance of IP lookups have been presented, but the good solution has not been came out. Software approach alleviates the memory usage, but at the same time it si slow in terms of searching speed when performing an IP lookup. Hardware approach, on the other hand, is fast, however, it has disadvantages of producing hardware overheads and high memory usage. In this paper, conventional researches on IP lookups are shown and their advantages and disadvantages are explained. In addition, by mixing two representative structures, a new hybrid parallel architecture for fast IP lookups is proposed. The performance evaluation result shows that the proposed architecture provides better performance and lesser memory usage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2B
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• pp.91-97
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• 2006

As increasing the network bandwidth, the threat of a network also increases with emerging various new services. For a high-performance network security, It is generally used that high-speed packet classification methods which employ hardware like TCAM. There needs an method using these devices efficiently because they are expensive and their capacity is not sufficient. In this paper, we propose an efficient packet classification using a Ternary-CAM(TCAM) which is widely used device for high-speed packet classification in which we have applied Snort rule set for the well-known intrusion detection system. In order to save the size of an expensive TCAM, we have eliminated duplicated IP addresses and port numbers in the rule according to the partitioning of a table in the TCAM, and we have represented negation and range rules with reduced TCAM size. We also keep advantages of low TCAM capacity consumption and reduce the number of TCAM lookups by decreasing the TCAM partitioning using combining port numbers. According to simulation results on our TCAM partitioning, the size of a TCAM can be reduced by upto 98$\%$ and the performance does not degrade significantly for high-speed packet classification with a large amount of rules.