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Design of Hybrid Parallel Architecture for Fast IP Lookups  

서대식 (연세대학교 전기·전자공학과)
윤성철 (연세대학교 전기·전자공학과)
오재석 (연세대학교 전기·전자공학과)
강성호 (연세대학교 전기·전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.5, 2003 , pp. 345-353 More about this Journal
Abstract
When designing network processors or implementing network equipments such as routers are implemented, IP lookup operations cause the major impact on their performance. As the organization of the IP address becomes simpler, the speed of the IP lookup operations can go faster. However, since the efficient management of IP address is inevitable due to the increasing number of network users, the address organization should become more complex. Therefore, for both IPv4(IP version 4) and IPv6(IP version 6), it is the essential fact that IP lookup operations are difficult and tedious. Lots of researcher for improving the performance of IP lookups have been presented, but the good solution has not been came out. Software approach alleviates the memory usage, but at the same time it si slow in terms of searching speed when performing an IP lookup. Hardware approach, on the other hand, is fast, however, it has disadvantages of producing hardware overheads and high memory usage. In this paper, conventional researches on IP lookups are shown and their advantages and disadvantages are explained. In addition, by mixing two representative structures, a new hybrid parallel architecture for fast IP lookups is proposed. The performance evaluation result shows that the proposed architecture provides better performance and lesser memory usage.
Keywords
High-speed IP lookup; Prefix; LPM(Longest Prefix Matching); Router; Low memory usage; Multiple CAM; Ternary CAM;
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