• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.1
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• pp.47-56
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• 2004

This paper describes a new bit allocation algorithm that can achieve a constant bit rate when coding multiple video objects, while improving rate-distortion (R-D) performance over the VM5 method for MPEG-4 object-based video coding. In particular, we propose two models to estimate the rate-distortion characteristics of coded objects as well as skipped objects. Based on the proposed models, we present several R-D coding modes with spatio-temporal trade-offs to improve coding efficiency. The proposed algorithm is performed at the object level for object-based video coding. Simulation results demonstrate moderate improvement at low as well as high bit rates. The proposed algorithm can produce the actual coded bits very close to the target bits over a wide range of bit rates. Consequently, the proposed algerian has not experienced any buffer overflow or underflow over the bit rates between 32 kbps and 256 kbps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.53-60
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• 2007

In a known plaintext scenario, fast correlation attack is very powerful attack on stream ciphers. Most of fast correlation attacks consider the cryptographic problem as the suitable decoding problem. In this paper, we introduce advanced multi-pass fast correlation attack which is based on the fast correlation attack, which uses parity check equation and Fast Walsh Transform, proposed by Chose et al. and the Multi-pass fast correlation attack proposed by Zhang et al. We guess some bits of initial states of the target LFSR with the same method as previously proposed methods, but we can get one more bits at each passes and we will recover the initial states more efficiently.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.307-314
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• 2003

In the general multiple video object coder, more interested objects such as speaker or moving object is consistently coded with higher priority. Since the priority of each object may not be fixed in the whole sequence and be variable on frame basis, it must be adjusted in a frame. In this paper, we analyze the independent rate control algorithm and global algorithm that the QP value is controled by the static parameters, object importance or priority, target PSNR, weighted distortion. The priority among static parameters is analyzed and adjusted into dynamic parameters according to the visual interests or importance obtained by camera interface. Target PSNR and weighted distortion are proportionally derived by using magnitude, motion, and distortion. We apply those parameters for the weighted distortion control and the priority-based control resulting in the efficient bit-rate distribution. As results of this paper, we achieved that fewer bits are allocated for video objects which has less importance and more bits for those which has higher visual importance. The duration of stability in the visual quality is reduced to less than 15 frames of the coded sequence. In the aspect of PSNR, the proposed scheme shows higher quality of more than 2d13 against the conventional schemes. Thus the coding scheme interfaced to human- eye proves an efficient video coder dealing with the multiple number of video objects.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1505-1512
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• 2009

This paper propose a new frame level rate control algorithm for improving video quality and decreasing quality variation of an entire video sequence in a very low bit rate environment. In the proposed scheme, the allocated bits to a GOP are distributed to each frame properly according to the frame characteristics as well as the buffer status and the channel bandwidth. The H.264 standard uses various coding modes and optimization methods to improve the compression performance, which makes it difficult to control the generated traffic accurately. In this paper, proper prediction models for low bit rate environments are lust proposed, and a target distortion is determined using the models. According to the target distortion, the bit budget is allocated to each frame. It is shown by experimental results that the new algorithm can generate the PSNR performance better than that of the existing rate control algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1014-1020
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• 2008

Storage devices such as memories are widely used in various electronic products. They require high-density memory and currently the data has been stored in multi-level format, that results in high error rate. In this paper, we apply error correction schemes that are widely used in communication system to the storage devices for satisfying low bit error rate and high code rate. In A WGN channel with average BER $10^{-5}$ and $5{\times}10^{-6}$, we study error correction schemes for 4-1evel cell to achieve target code rate 0.99 and target BER $10^{-11}$ and $10^{-13}$, respectively. Since block codes may perform better than the concatenated codes for high code rate, and it is important to use less degraded inner code even when many bits are punctured. The performance of concatenated codes using general feedforward systematic convolutional codes are worse than the block code only scheme. The simulation results show that RSC codes must be used as inner codes to achieve good performance of punctured convolutional codes for high code rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.453-461
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• 2010

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered $0.18{\mu}m$ technology library is reduced by 16%.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.134-141
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• 2019

Radar systems are divided into the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar depending on the transmission waveform. In particular, the PD radar is advantageous for long-range target detection, and the FMCW radar is suitable for short-range target detection. In this paper, we present design and implementation results for a multi-mode radar signal processor (RSP) that can support both PD and FMCW radar systems to detect unmanned aerial vehicles (UAVs) at short distances as well as long distances. The proposed radar signal processor can be implemented based on Altera Cyclone-IV FPGA with 19,623 logic elements, 9,759 registers, and 25,190,400 memory bits. The logic elements and registers of the proposed radar signal processor are reduced by approximately 43% and 30%, respectively, compared to the sum of logic elements and registers of the conventional PD radar and FMCW radar signal processor.

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2118-2126
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• 2017

The large-scale power system blackouts have indicated that conventional protection relays that based on local signals cannot fit for modern power grids with complicated setting or heavily loaded-flow transfer. In order to accurately detect various faulted lines and improve the fault-tolerance of wide-area protection, a novel multi-section weighed fault matching and detecting algorithm is proposed. The real protection vector (RPV) and expected section protection vectors (ESPVs) for five fault sections are constructed respectively. The function of multi-section weighed fault matching is established to calculate the section fault matching degrees between RPV and five ESPVs. Then the fault degree of protected line based on five section fault degrees can be obtained. Two fault detecting criterions are given to support the higher accuracy rate of detecting fault. With the enumerating method, the simulation tests illustrate the correctness and fault-tolerance of proposed algorithm. It can reach the target of 100% accuracy rate under 5 bits error of wide-area protections. The influence factors of fault-tolerance are analyzed, which include the choosing of wide-area protections, as well as the topological structures of power grid and fault threshold.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.583-585
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• 1999

This paper presents the controller of multiple DC motors using the network. This controller has been built with 16-bits one chip microprocessor (87C196CA) which includes the integrated CAN serial communication and position control for two motors. Since only one microprocessor is needed, the proposed controller is not only cost effective but also powerful. The system is composed of one main controller, trajectory planner, and the other sub controller, position controller. The main controller which has been built using Visual Basic programming on the Pentium PC, generates the trajectory and then transmits it to the sub controller. The trajectory transmitted from the PC will be processed by the sub controller. Two motors are controlled using the conventional position control, PID, to reach them the same target position but with different velocities at the same time. The communications between the main controller and sub controller is performed through the RS-232 or the CAN communication The CAN would be safer and faster than serial communication network since it has non-destructive bitwise arbitration specification. In this paper, we consider the CAN communications generally and then show the usefulness of the proposed controller by demonstrating position control of two DC motors.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.10
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• pp.1814-1829
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• 2011

In this paper, we present a model-based video bit rate estimation scheme for reducing the bit rate while maintaining a given target quality in many video streaming services limited by network bandwidth, such as IPTV services. Each item of video content can be stored on a video streaming server and delivered with the estimated bit rate using the proposed scheme, which consists of the following two steps: 1) In the first step, the complexity of each intra-frame in a given item of video content is computed as a frame feature to extract a group of candidate frames with a lot of bits. 2) In the second step, the bit rate of the video content is determined by applying statistical analysis and hypothesis testing to that group. The experimental results show that our scheme can reduce the bit rate by up to 78% with negligible degradation of subjective quality, especially with the low-complexity videos commonly used in IPTV services.