• Title/Summary/Keyword: Tae-um

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Inhibitory Effect of Coumarins on Nitric Oxide Production in LPS-Activated Murine Macrophages (쿠마린에 의한 RAW 264.7 세포주의 Nitric Oxide 생성 저해활성)

  • Rho, Tae-Cheol;Choi, Hee-Cheol;Kim, Bo-Yeon;Kim, Young-Ho;Ahn, Jong-Seog;Kim, Young-Kook;Lee, Hyun-Sun
    • Korean Journal of Pharmacognosy
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    • v.30 no.4
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    • pp.413-416
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    • 1999
  • During the screening for inhibitors on nitric oxide (NO) production in LPS-activated murine macrophage, RAW 264.7 cells, two coumarins were isolated from chloroform extract of Ponciri Fructus. They were identified as imperatorin (10), phellopterin (11) on the basis of spectroscopic methods. The $IC_{50}$ values for NO formatiom were about $5.4\;{\um}M$ and $35.0\;{\um}M$, respectively, and then eleven coumarins were tested for the inhibitory effects on NO production in activated macrophages. All the test coumarins inhibited NO production in concentration-dependent manner and furanocoumarins (6-11) showed much more potent inhibitory effect than simple coumarins. Among the compounds examined xanthotoxin (8) was the most potent inhibitors of NO production $(IC_{50}=1.4\;{\mu}M)$. Analysis of the structure-activity relationship among these coumarins led to the conclusion that the substitution of C-5 position in furanocoumarins reduces greatly their inhibitory potency although the substitution of C-8 does not almost affect it.

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Design of Variable Gain Low Noise Amplifier with Memory Effects Feedback for 5.2 GHz Band (5.2 GHz 대역에서 동작하는 기억 기능 특성을 갖는 궤환 회로를 이용한 변환 이득 저잡음 증폭기 설계)

  • Lee, Won-Tae;Jeong, Ji-Chai
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.1
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    • pp.53-60
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    • 2010
  • This paper presents a novel gain control system composed of a feedback circuit, Two stage Low Noise Amplifier (LNA) using 0.18 um CMOS technology for 5.2 GHz. The feedback circuit consists of the seven function blocks: peak detector, comparator, ADC, IVE(Initial Voltage Elimination) circuit, switch, storage, and current controller. We focus on detecting signal and designing storage circuit that store the previous state. The power consumption of the feedback circuit in the system can be reduced without sacrificing the gain by inserting the storage circuit. The adaptive front-end system with the feedback circuit exhibits 11.39~22.74 dB gain, and has excellent noise performance at high gain mode. Variable gain LNA consumes 5.68~6.75 mW from a 1.8 V supply voltage.

Automatic Registration Method for EO/IR Satellite Image Using Modified SIFT and Block-Processing (Modified SIFT와 블록프로세싱을 이용한 적외선과 광학 위성영상의 자동정합기법)

  • Lee, Kang-Hoon;Choi, Tae-Sun
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.3
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    • pp.174-181
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    • 2011
  • A new registration method for IR image and EO image is proposed in this paper. IR sensor is applicable to many area because it absorbs thermal radiation energy unlike EO sensor does. However, IR sensor has difficulty to extract and match features due to low contrast compared to EO image. In order to register both images, we used modified SIFT(Scale Invariant Feature Transform) and block processing to increase feature distinctiveness. To remove outlier, we applied RANSAC(RANdom SAample Concensus) for each block. Finally, we unified matching features into single coordinate system and remove outlier again. We used 3~5um range IR image, and our experiment result showed good robustness in registration with IR image.

Design and Comparison of the Fast-Hopping Frequency Synthesizers for MB-OFDM UWB Systems (MB-OFDM 방식의 UWB 시스템을 위한 Fast-Hopping 주파수 합성기의 유형별 설계 및 비교)

  • Lee, Jae-Kyoung;Park, Joon-Kyu;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.12
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    • pp.2264-2270
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    • 2006
  • This paper describes fast-hewing frequency synthesizers for multi-band OFDM(MB-OFDM) ultra-wide band(UWB) systems. Three different structures in generating 3 center frequencies(3432MHz, 3960MHz, 4488MHz) are designed and compared. The first structure generates 3 center frequencies using only one PLL operating at 4224MHz, and the second uses three PLLs operating at corresponding center frequencies. The proposed third structure employes two PLLs operating at 3960MHz and 528MHz. Simulation results using 0.18um RF CMOS process parameters show that the third structure exhibits boner characteristics in spur, area and current consumption than the other structures. The band switching time of the proposed synthesizer is less than 1.In and the spur is less than -36dBc. The synthesizer consumes 22mA from a 1.8V supply.

Pathogenesis Study of Oriental OB & GY Questionnaires (한방부인과 진단용 설문지의 병기 연구)

  • Lee In Sun;Jean Ran Hee;Cha Hye Suk;Bae Kyung Mi;Kim Mi Jin;Lee Yong Tae;Ji Gyu Yang;Kim Jong Won
    • Journal of Physiology & Pathology in Korean Medicine
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    • v.18 no.2
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    • pp.401-407
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    • 2004
  • Purpose : This study investigated reliability of Oriental DB & GY(obstetrics & gynecology) Questionnaires's items which was used by Dong-Eui OB & GY through analysis of oriental OB & GY books. Method : This study investigated differentiation of syndrome through analysis of oriental OB & GY book's. Result: This study investigated differentiation of syndrome through analysis of oriental OB & GY disease and pathogenesis. This study's pathogenesis was such that deficiency of Ki, deficiency of blood, stagnation of Ki, stagnated blood, deficiency of Yang, deficiency of Um, cold syndrome, heat syndrome, dampness, dryness, phlegm, kidney, liver, heart, spleen, wind, lung. We except lung from Questionnaires's pathogenesis because it is stuck for importance. We except wind from Questionnaires's pathogenesis because it is stuck for preguence. Oriental OB & GY Questionnaires's pathogenesis consist of 15 items such that deficiency of Ki, deficiency of blood, stagnation of Ki, stagnated blood, deficiency of Yang, deficiency of Um, cold syndrome, heat syndrome, dampness, dryness, phlegm, kidney, liver, heart, spleen. Oriental OB & GY Questionnaires construct pathogenesis's question and guide post through we examined it's reasonableness.

CMOS ROIC for MEMS Acceleration Sensor (MEMS 가속도센서를 위한 CMOS Readout 회로)

  • Yoon, Eun-Jung;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.18 no.1
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    • pp.119-127
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    • 2014
  • This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor ${\Sigma}{\Delta}$ modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and ${\Sigma}{\Delta}$ modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

A New Design of High-Speed 1-Bit Full Adder Cell Using 0.18${\mu}m$ CMOS Process (0.18${\mu}m$ CMOS 공정을 이용한 새로운 고속 1-비트 전가산기 회로설계)

  • Kim, Young-Woon;Seo, Hea-Jun;Cho, Tae-Won
    • Journal of IKEEE
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    • v.12 no.1
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    • pp.1-7
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    • 2008
  • With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

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The Analysis of Total Ionizing Dose Effects on Analog-to-Digital Converter for Space Application (우주용 ADC의 누적방사선량 영향 분석)

  • Kim, Tae-Hyo;Lee, Hee-Chul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.6
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    • pp.85-90
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    • 2013
  • In this paper, 6bit SAR ADC tolerant to ionizing radiation is presented. Radiation tolerance is achieved by using the Dummy Gate Assisted (DGA) MOSFET which was proposed to suppress the leakage current induced by ionizing radiation and its comparing sample is designed with the conventional MOSFET. The designed ADC consists of binary capacitor DAC, dynamic latch comparator, and digital logic and was fabricated using a standard 0.35um CMOS process. Irradiation was performed by Co-60 gamma ray. After the irradiation, ADC designed with the conventional MOSFET did not operate properly. On the contrary, ADC designed with the DGA MOSFET showed a little parametric degradation of which DNL was increased from 0.7LSB to 2.0LSB and INL was increased from 1.8LSB to 3.2LSB. In spite of its parametric degradation, analog to digital conversion in the ADC with DGA MOSFET was found to be possible.

A Study on the Improvement for a Defect Diagnosis of Track Circuit on HSL (고속선 궤도회로 결함진단을 위한 개선방안 연구)

  • Park, Ki-Bum;Lee, Tae-Hoon;Lee, Gi-Chun
    • Proceedings of the KSR Conference
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    • 2007.05a
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    • pp.1656-1664
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    • 2007
  • This paper introduces a study of improvement for a defect diagnosis of the UM71C track circuit using on HSL. The track circuit on HSL has long operation section. Therefore, when the worker maintain, many times and efforts are spent. So, periodically, we have operated a inspection car. However, we don't know exactly the state changed of the inspection data when track circuit has defect. Actually, We fixed a sample area within operation section on HSL and performed the simulations for short circuit current that is reflected characteristic impedance and propagation factor. We compared the measuring data with the result of the simulation. Using verified simulation program, we estimated inspection data as the malfunction number and the change of capacity of compensation capacitor. These study need to secure of the safety as the train operation. Also, It needs to make a criteria of analysis for the maintenance through comparison simulation data and inspection data.

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Dual Mode Buck Converter Capable of Changing Modes (모드 전환 제어 가능한 듀얼 모드 벅 변환기)

  • Jo, Yong-min;Lee, Tae-Heon;Kim, Jong-Goo;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.10
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    • pp.40-47
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    • 2016
  • In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.