• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.857-858
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• 2011

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.745-746
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• 2011

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.226-235
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• 2016

The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.23-29
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• 2014

Less power consumption, lower cost, smaller size and more functionality are the increasing demands for consumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet this requirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. This study discribe the thermal stress reliability trend for successful implementation of 3-D packaging.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.179-179
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• 2011

관통전극(TSV, Trough Silicon Via) 기술은 전자부품의 소형화, 고성능화, 생산성 향상을 이룰 수 있는 기술이다. Cu는 현재 배선 기술에 적용되고 있고 전기적 저항이 낮아서 TSV filling 재료로 사용된다. 하지만 확산 방지막에 의해 완벽히 감싸지지 않는다면, Cu+은 빠르게 절연막을 통과하여 Si 웨이퍼로 확산된다. 이런 현상은 절연막의 누설과 소자의 오동작 등의 신뢰성 문제를 일으킬 수 있다. 현재 TSV의 제조와 열 및 기계적 응력에 관한 연구는 활발히 진행되고 있으나 Biased-Thermal Stress(BTS) 조건하의 Cu 확산에 관한 연구는 활발하지 않는 것이 실정이다. 이를 위해 본 연구에서는 TSV용 Cu 확산 방지막 Ti에 대해 Cu+의 drift 억제 특성을 조사하였다. 실험을 위해 Cu/확산 방지막/Thermal oxide/n-type Si의 평판 구조를 제작하였고 확산 방지막의 두께에 따른 영향을 조사하기 위해 Ti의 두께를 10 nm에서 100 nm까지 변화하였으며 기존 Cu 배선 공정에서 사용되는 확산 방지막 Ta와 비교하였다. 그리고 Cu+의 drift 측정을 위해 Biased-Thermal Stress 조건(Thermal stress: $275^{\circ}C$, Bias stress: +2MV/cm)에서 Capacitance 및 Timedependent dielectric breakdown(TDDB)를 측정하였다. 그 결과 Time-To Failure(TTF)를 이용하여 Cu+의 drift를 측정할 수 있었으며, 확산 방지막의 두께가 증가할수록 TTF가 증가하였고 물질에 따라 TTF가 변화하였다. 따라서 평판 구조를 이용한 본 실험의 Cu+의 drift 측정 방법은 향후 TSV 구조에서도 적용 가능한 방법으로 생각된다.

• ETRI Journal
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• v.41 no.3
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• pp.396-407
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• 2019

Laser-assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single-tier LAB process for 3D through-silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single-tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu-Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.127-132
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• 2019

In this study, the fabrication of through-silicon vias (TSVs) filled with SWNTs/Sn by utilizing surface/bulk micromachining and MEMS technologies is proposed. Tin (Sn) and single-walled nanotube (SWNT) powders are used as TSV interconnector materials in the development of a novel TSV at low temperature. The measured resistance of a TSV filled with SWNT/Sn powder is considerably reduced by increasing the fraction of Sn and is lower than that of a TSV filled with only Sn. This is because of a decrease in the surface scattering of electrons along with an increase in the grain size of sintered SWNTs/Sn. The proposed method is conducted at low temperatures (< $400^{\circ}C$) due to the low melting temperature of Sn; hence, the proposed TSVs filled with SWNTs/Sn can be utilized in CMOS based applications.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.374-378
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• 2012

In an effort to overcome the problems which arise when fabricating high-aspect-ratio TSV(through silicon via), we performed experiments involving the void-free Cu filling of a TSV(10~20 ${\mu}m$ in diameter with an aspect ratio of 5~7) by controlling the plating DC current density and the additive SPS concentration. Initially, the copper deposit growth mode in and around the trench and the TSV was estimated by the change in the plating DC current density. According to the variation of the plating current density, the deposition rate during Cu electroplating differed at the top and the bottom of the trench. Specifically, at a current density 2.5 mA/$cm^2$, the deposition rate in the corner of the trench was lower than that at the top and on the bottom sides. From this result, we confirmed that a plating current density 2.5 mA/$cm^2$ is very useful for void-free Cu filling of a TSV. In order to reduce the plating time, we attempted TSV Cu filling by controlling the accelerator SPS concentration at a plating current density of 2.5 mA/$cm^2$. A TSV with a diameter 10 ${\mu}m$ and an aspect ratio of 7 was filled completely with Cu plating material in 90 min at a current density 2.5 mA/$cm^2$ with an addition of SPS at 50 mg/L. Finally, we found that TSV can be filled rapidly with plated Cu without voids by controlling the SPS concentration at the optimized plating current density.