• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.80-80
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• 2018

실리콘 관통전극 (Through Silicon Via, TSV)는 메모리 칩을 적층하여 고밀도의 집적회로를 구현하는 기술로, 기존의 와이어 본딩 (Wire bonding) 기술보다 낮은 소비전력과 빠른 속도가 특징인 3차원 집적기술 중 하나이다. TSV는 일반적으로 도금 공정을 통하여 충전되는데, 고종횡비의 TSV에 결함 없이 구리를 충전하기 위해서 3종의 유기첨가제(억제제, 가속제, 평탄제)가 도금액에 첨가되어야 한다. 이러한 첨가제 중 결함 발생유무에 가장 큰 영향을 주는 첨가제는 평탄제이기 때문에, 본 연구에서는 이미다졸(imidazole) 계열, 이민(imine) 계열, 디아조늄(diazonium) 계열 및 피롤리돈(pyrrolidone) 계열과 같은 평탄제(leveler)의 작용기에 따라 TSV 충전 성능을 조사하였다. TSV 충전 시 관능기의 거동을 규명하기 위해 QCM (quartz crystal microbalance) 및 EQCM (electrochemical QCM)을 사용하여 흡착 정도를 측정하였다. 실험 결과, 디아조늄 계열의 평탄제는 TSV를 결함 없이 충전하였지만 다른 작용기를 갖는 평탄제는 TSV 내 결함이 발생하였다. QCM 분석에서 디아조늄 계열의 평탄제는 낮은 흡착률을 보이지만 EQCM 분석에서는 높은 흡착률을 나타내었다. 즉, 디아조늄 계열의 평탄제는 전기 도금 동안 전류밀도가 집중되는 TSV의 상부 모서리에서 국부적인 흡착을 선호하며 이로 인하여 무결함 충전이 달성된다고 추론할 수 있다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.39-46
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• 2016

저전력화, 고성능화, 경박단소화로 발전해 나가는 전자산업의 트렌드에 부합하는 기술로 TSV는 진보된 3D IC에서 널리 사용되어질 가장 잠재력이 큰 기술이다. 미세공정의 한계에 근접하고 있는 만큼 그동안 전 세계 유수의 반도체 업체들과 연구소들이 TSV의 공정기술 및 전기적 성능을 향상시키기 위한 많은 노력을 기울이고 있다. 이러한 노력은 차원 Scaling의 한계 극복한 차세대 전자패키지 및 모듈 기술 분야의 원천 기술을 확보함으로써 관련 산업 분야의 기술 선도가 가능하고 초소형/고성능 시스템 및 부품 개발로 관련 지적 재산 획득이 가능하며, 국제적 전자산업 경쟁 우위를 유지하고, 새로운 시장 창출 및 시장 선점하기 위한 것이다. 본 글에서 기본적인 TSV 형성을 위한 공정기술에 대해 소개하였고, TSV를 등가회로로 표현하고, 전기적 성능을 빠르게 예측하기 위한 내용을 언급하였다. 또한 TSV 기술의 국내외 연구동향을 소개하면서 향후 반도체 시장에서 TSV 기술이 시장의 주도권을 쥔다고 할 수 있을 만큼, 앞으로도 3D 패키징에 대한 연구개발이 지속적일 것으로 기대한다.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• Journal of Welding and Joining
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• v.31 no.3
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• pp.11-16
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• 2013

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.753-754
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• 2011

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.27-31
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• 2015

Thermal management becomes a key technology as the power density of high performance and high density devices increases. Conventional heat sink or TIM methods will be limited to resolve thermal problems of next-generation IC devices. Recently, to increase heat flux through high powered IC devices liquid cooling system has been actively studied. In this study a chip-level liquid cooling system with TSV and microchannel was fabricated on Si wafer using DRIE process and analyzed the cooling characteristics. Three different TSV shapes were fabricated and the effect of TSV shapes was analyzed. The shape of liquid flowing through microchannel was observed by fluorescence microscope. The temperature differential of liquid cooling system was measured by IR microscope from RT to $300^{\circ}C$.

• Journal of Welding and Joining
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• v.29 no.1
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.