• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.121-124
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• 2009

In this paper, the techniques and design focus of flexible gain coltrol of LAN(Low Noise Amplifier) using the TSMC 0.18um CMOS process. The design frequency set up a standard on 2.4GHz that is used in Zigbee system. The design concepts a basic Cascode LNA techniques and a swiching circuit consisted of 4 NMOS of load resistance, which convert the output impedenceby tuning on or off. The result show the gain change by NMOS operated swich. The simulation result is that Gain is 14.07dB-16.79dB and NF(Noise Figure) is 1.06dB-1.09dB.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.348-351
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• 2001

In this paper, the Gm-C filter for low voltage and low power applications using a fully-differential transconductor is presented. The designed transconductor using the series composite transistors and the low voltage composite transistors has wide input range at low supply voltage. A negative resistor load (NRL) technology for high DC gain of the transconductor is employed with a common mode feedback(CMFB). As a design example, the third-order Elliptic lowpass filter is designed. The designed filter is simulated and examined by HSPICE using TSMC $0.35{\mu}m$ CMOS n-well parameters. The simulation results show 138kHz cutoff frequency and 11.05mW power dissipation with a 3.3V supply voltage.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.417-418
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• 2008

A quadrature voltage controlled oscillator(QVCO) with MOS-varactors has been fabricated for X-band applications. The QVCO consists of two cross -coupled differential cores and buffer amplifiers, which has fabricated in TSMC $0.18{\mu}m$ CMOS process. The QVCO exhibits a frequency tuning range from 8.38 GHz to 10.62 GHz. The phase noise is -88 dBc/Hz at 1 MHz-offset frequency. The total bias current is 25 mA including four buffer amplifiers.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.437-438
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• 2008

This paper proposes a 8th-order single loop band-pass sigma-delta modulator that satisfies a wide bandwidth of 6MHz, which is required for a HDTV application. The proposed architecture is based on a simple analog structure that enlarges the noise shaping with a low OSR. In addition, a feedforward scheme is used to relax op-amp performance requirements. The proposed modulator has been simulated using the 0.18um 1.8v TSMC technology. The simulation results show that the bandwidth is 6MHz and SNQR is 70dB.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.439-440
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• 2008

A high-speed DCO is proposed that uses the negative-skewed delay scheme. The DCO consists of a ring of inverters with each PMOS transistor driven from the output of 3 earlier stage through a set of minimum-sized pass-transistors. The digitization of negative-skewed delay is achieved by selecting pass-transistors turned on and digitizing the gate voltages of the selected pass-transistors. The proposed 7-stage DCO has been simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS process to obtain a resolution of 3ps and an operation range of 2.88-5.03GHz.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.529-530
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• 2008

The proposed CMOS Quadrature VCO for WLAN application was designed in TSMC $0.18\;{\mu}m$ RF CMOS technology. The QVCO based on NMOS back-gate as a coupling transistor and switched capacitors array without tail transistors is designed to generate quadrature output signals. The simulated results show that the QVCO core consumed 3.67 mA and 6.6 mW from a 1.8 V supply. The QVCO is tunable between $4.76\;GHz\;{\sim}\;6.35\;GHz$ and has a phase noise lower than -116.8 ㏈c/Hz at 1 MHz offset over the entire tuning range

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2257-2261
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• 2007

A new CMOS transresistance amplifier for low-voltage analog integrated circuit design applications is presented. The proposed transresistance amplifier circuit based on common-source and negative feedback topology is compared with other recent reported transresistance amplifier. The proposed transresistance amplifier achieves high transresistance gain, gain-bandwidth with the same input/output impedance and the minimum supply voltage $2V_{DSAT}+V_T$. Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS technology was performed and achieved $59dB{\Omega}$ transresistance gain which is above the maximum about $18dB{\Omega}$ compared to transresistance gain of the reported circuit.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.255-259
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• 2008

In this paper, a current-mode integrator for low-voltage, low-power analog integrated circuits is presented. Using the proposed current-mode integrator, the baseband analog filter is designed for WCDMA wireless communication. To verify the proposed current-mode integrator circuit, Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS parameter is performed and achieved 44.9dB gain, 15.7MHz unity gain frequency. The described 3rd-order current-mode baseband analog filter is composed of the proposed current-mode integrator, and SFG(Signal Flow Graph) method is used to realize the baseband filter. The simulated results show 2.12MHz cutoff frequency which is suitable for WCDMA baseband block.