• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.26-32
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• 2003

Then-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) method on glass were measured to obtain the electrical parameters such as of I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. Then, devices were analyzed to obtain the reliability and appliability on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 5$\mu\textrm{m}$/2$\mu\textrm{m}$, 8$\mu\textrm{m}$, 30$\mu\textrm{m}$ devices of channel width/length, the field effect mobilities are 111, 116, 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus. the poly-Si TFT's used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate the display panel and peripheral circuit on a targe glass substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.322-325
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• 2000

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.1131-1134
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• 2003

A low temperature doping technique has been studied for application in poly-Si TFT's on plastic substrates. Heavily-doped amorphous silicon layers were deposited on poly-Si and the dopant atoms were driven in by subsequent excimer laser annealing. The entire process was carried out under a substrate temperature of $120^{\circ}C$, and a sheet resistance as low as $300 {\Omega}/sq$. was obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.393-394
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• 2004

To get rid of cell assembly margin and have more process room of upper substrate, we developed truly COT (Color Filter On TFF Array) LCDs in that B/M (Black Matrix) as well as C/F (Color Filter) layer is located on TFT substrate. Novel B/M material is also developed for this COT structure. Difficulty in making contact hole through C/F layer was solved by making each C/F pattern isolated from others. We think this configuration will be core technology for prominent COT LCDs.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.1
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• pp.26-29
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• 2006

Transparent ZnO thin films were prepared by KrF pulsed laser deposition (PLD) technique and applied to a bottom-gate type thin film transistor device as an active channel layer. A high conductive crystalline Si substrate was used as an metal-like bottom gate and SiN insulating layer was then deposited by LPCVD(low pressure chemical vapour deposition). An aluminum layer was then vacuum evaporated and patterned to form a source/drain metal contact. Oxygen partial pressure and substrate temperature were varied during the ZnO PLD deposition process and their influence on the thin film properties were investigated by X-ray diffraction(XRD) and Hall-van der Pauw method. Optical transparency of the ZnO thin film was analyzed by UV-visible phometer. The resulting ZnO-TFT devices showed an on-off ration of $10^6$ and field effect mobility of 2.4-6.1 $cm^2/V{\cdot}s$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.445-446
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• 2005

This letter reports the fabrication of polycrystalline silicon thin-film transistors (poly-Si TFT) on flexible plastic substrates using amorphous silicon (a-Si) precursor films by sputter deposition. The a-Si films were deposited with mixture gas of argon and helium to minimize the argon incorporation into the film. The precursor films were then laser crystallized using XeCl excimer laser irradiation and a four-mask-processed poly-Si TFTs were fabricated with fully self-aligned top gate structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.41-41
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• 2009

We utilized atomic layer deposition (ALD) for the growth of the ZnO channel layers in the oxide thin-film-transistors (TFTs) with a bottom-gate structure using a $SiO_2/p-Si$ substrate. For fundamental study, the effect of the channel thickness and thermal treatment on the TFT performance was investigated. The growth modes for the ALD grown ZnO layer changed from island growth to layer-by-layer growth at thicknesses of > 7.5 nm with highly resistive properties. A channel thickness of 17 nm resulted in the good TFT behavior with an onloff current ratio of > $10^6$ and a field effect mobility of 2.9 without the need for thermal annealing. However, further increases in the channel thickness resulted in a deterioration of the TFT performance or no saturation. The ALD grown ZnO layers showed reduced electrical resistivity and carrier density after thermal treatment in oxygen.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.7
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• pp.525-531
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• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.205-207
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• 2008

The new process for hybrid silicon thin film transistor (TFT) using DPSS laser has been developed for realizing both low-temperature poly-Si (LTPS) TFT and a-Si:H TFT on the same substrate as a backplane of active matrix liquid crystal display. LTPS TFTs are integrated on the peripheral area of the panel for gate driver integrated circuit and a-Si:H TFTs are used as a switching device for pixel in the active area. The technology has been developed based on the current a-Si:H TFT fabrication process without introducing ion-doping and activation process and the field effect mobility of $4{\sim}5\;cm^2/V{\cdot}s$ and $0.5\;cm^2/V{\cdot}s$ for each TFT was obtained. The low power consumption, high reliability, and low photosensitivity are realized compared with amorphous silicon gate driver circuit and are demonstrated on the 14.1 inch WXGA+ ($1440{\times}900$) LCD Panel.