• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.538-542
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• 1999

New methodology of parameter calibration is proposed for TCAD simulation of nMOSFET in ESD(Electro-Static Discharge) protection circuits. Recently, TLP(Transmission Line Pulsing) measurement has received great interest due to the ability of analyzing device characteristics when ESD pulse is applied to the ESD pulse is applied to the ESD protection circuits. This paper describes new methodology of analyizing TLP measurement, TCAD simulation, and parameter calibration.

• Journal of IKEEE
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• v.25 no.4
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• pp.778-781
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• 2021

In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.321-324
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• 2001

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased packing density. This paper has compared Micro-Tec with ISE-TCAD. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths 180nm. We have presented MOSF ET's characteristics such as I-V characteristic, electric field. and compared with Micro-Tec and ISE-TCAD.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.136-141
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• 2023

The continuous shrinking of transistors in integrated circuits leads to difficulties in improving performance, resulting in the emerging transistors such as nanosheet field-effect transistors. In this paper, we propose a TCAD-machine learning framework of nanosheet FETs to model the current-voltage characteristics. Sentaurus TCAD simulations of nanosheet FETs are performed to obtain a large amount of device data. A machine learning model of I-V characteristics is trained using the multi-layer perceptron from these TCAD data. The weights and biases obtained from multi-layer perceptron are implemented in a PSPICE netlist to verify the accuracy of I-V and the DC transfer characteristics of a CMOS inverter. It is found that the proposed machine learning model is applicable to the prediction of nanosheet field-effect transistors device and circuit performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.490-493
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• 2000

The technology for characteristics analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high integrated device by computer simulation and to fabricate the device having such characteristics became one of very important subjects. As devices become smaller to submicron, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane by TCAD(Technology Computer Aided Design) to develop optimum device structure. We compared and analyzed the characteristics of such device structure, i.e., impact ionization, electric field and I-V characteristics curve with lightly-doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.103-108
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• 2002

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade In response to the constant demand for increased speed, decreased power, and increased packing density. The state -of-the-art simulation programs are developed by engineers and scientists. This paper has compared commercial programs of Micro-tec and ISE-TCAD in device simulation. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths(Lg) 180㎚. We have presented MOSFET's characteristics such as I-V characteristic and electric field, and compared Micro-tec with ISE TCAD.

• Journal of the Korea Society for Simulation
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• v.22 no.4
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• pp.93-98
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• 2013

In this paper, the proposed shallow trench isolation structures for high threshold voltage for very large scale and ultra high voltage integrated circuits MOSFET were simulated. Physically based models of hot-carrier stress and dielectric enhanced field of thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated devices over an extended range of stress biases and ambient temperatures. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.3
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• pp.177-182
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• 2003

In the case of the flash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must be processed. In this study, an efficient design flow is suggested using TCAD tools. The test vehicle is replaced with well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for flash memory device. The calibration errors are less than 5% of a full chip operation, which is accepted by the designers. The results of the calibration were used to predict I-V curves and model parameter of the various transistors for the design of flash device.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1182-1187
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• 2013

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.59-63
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• 2005

A simulation method combined with the simulation program with integrated circuit emphasis (SPICE) and the technology computer-aided design (TCAD) has been proposed to estimate the electrical characteristics of the metal-ferroelectric-semiconductor field effect transistor (MFS/MFISFET). The complex behavior of the ferroelectric property was analyzed and surface potential of the channel region in the MFS gate structure was calculated with the numerical TCAD method. Since the calculated surface potential is equivalent with the surface potential obtained with the SPICE model of the conventional MOSFET, we can obtain the current-voltage characteristics of MFS/MFISFET corresponding to the applied gate bias. Therefore, the proposed method will be very useful for the design of the integrated circuits with MFS/MFISFET memory cell devices.