• ETRI Journal
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• 제45권1호
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• pp.171-179
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• 2023

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13㎛-0.16㎛ to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

• 센서학회지
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• 제29권4호
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• pp.275-278
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• 2020

In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field-Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating and the high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthreshold swing of 80 mV/decade for drain voltage (V_DS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, the subthreshold swing at gate voltage (V_GS) = threshold voltage (V_T), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.

• Design & Manufacturing
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• 제14권1호
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• pp.15-21
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• 2020

Smart systems in different application areas such as automotive, medical and consumer electronics require a novel manufacturing method of electronic, optical and mechanical functions into products. Traditional methods including mechanical assembly, bonding of plastic and electronic circuit cause the problems in large size of products and complicated manufacturing processes. In this study, thermoforming and film insert molding were applied to fabricate a dome shaped plastic part embedded with electronic circuits. The deformation of patterns printed on PET film was predicted by thermoforming simulation using T-SIM, and the results were compared with those by experiment. In order to decrease spring-back after thermoforming, the Taguchi method of design of experiment was used. Through ANOVA analysis, it was found that mold temperature was the most dominant parameter for spring-back. By using flow analysis, gate design was performed to decrease injection pressure. During film insert molding, the wash-out of ink printed on film occurred for Polycarbonate. When the resin was changed to PMMA, the wash-out disappeared due to low melt temperature.

• ETRI Journal
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• 제38권4호
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• pp.675-684
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• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• 전자공학회논문지D
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• 제36D권1호
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• pp.38-46
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• 1999

본 논문에서는 0.25${\mu}m$ T형 게이트 P-HEMT의 제작 및 특성 평가를 하였고, 제작된 P-HEMT를 X-밴드용 3단 MMIC 저잡음 증폭기 설계에 응용하였다.제작된 P-HEMT의 DC 특성은 최대 외인정 전달 컨덕턴스가 400mS/mm이고, 최대 드레인 전류는 400mA/mm이었다. RF 및 잡음 특성은 전류 이등 차단 주파수($f_T$)가 65GHz이고, 주파수 9GHz에서 최소 잡음 지수는 0.7dB, 관련 이득은 14.8dB이었다. 이때의 바이어스 조건은 Vds가 2V이고, Ids는 60%Idss이었다. 저잡음 증폭기 설계에 있어서, 회로 Topology는 인덕턴스 직렬 궤환(Series Feedback)으로 쇼토 스터브(Short Stub)를 사용하였다. 이때 최적의 쇼트 스터브 길이를 찾기 위해, 직렬 궤환에 의한 잡음 지수와 이득 특성, 그리고 안정성에 대한 영향을 조사하였다. 설계된 회로의 특성은 주파수 8.9-9.5GHz에서 이득이 33dB이상, 잡음 지수가 1.2dB이하, 그리고 입출력 반사 계수가 각각 15dB와 14dB이하로 우수한 성능을 보였다. 따라서 제작된 소자가 고이득 X-밴드용 저잡음 증록기에 매우 적합한 소자임을 확인할 수 있었다.

• 한국주조공학회지
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• 제20권6호
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• pp.368-376
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• 2000

Rheology forming technology has been accepted as a new method for fabricating near net shaped products with lightweight aluminum alloys. The rheology forming process consists of reheating process of billet, billet handling, filling into the die cavity and solidification of rheology formed part. The rheology forming experiments are performed with two different die temperatures ($T_d$ = $200^{\circ}C$, $300^{\circ}C$) and orifice gate type. The filling behavior and various defects of Al-Si materials with wear resistance (A357, A390 and ALTHIX 86S) fabricated in rheology forming process are evaluated in terms of alloying elements and surface non-uniformity. Finally, the methods to obtain the rheology formed products with high quality are described by solutions for avoiding the surface and internal defects.

• 대한전자공학회논문지SD
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• 제37권3호
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• pp.34-38
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• 2000

본 논문에서는 AlGaAs/lnGaAs/GaAs P-HEMT 소자를 이용한 10 Gb/s 광수신기용 MMIC 초고속 저잡음 전치증폭기를 설계, 제작하고 특성을 분석 하였다. T 형태의 0.15㎛ 게이트 길이를 갖는 P-HEMT 소자를 이용하여 3단 트랜스임피던스 구조로 회로를 설계하였으며 광대역 특성을 얻기 위하여 피킹인덕터를 사용하였고, 저잡음특성을 위하여 게이트폭을 최적화하였다. 제작된 전치증폭기는 트랜스임피던스 이득 60㏈Ω, 대역폭 9.15 ㎓, 잡음지수가 3.9 ㏈ 이하인 특성을 보였다.

• Journal of electromagnetic engineering and science
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• 제1권1호
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• pp.73-77
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• 2001

We studied the fabrication of GaAs-based pseudomorphic high electron mobility transistors(PHEMT`s) for the purpose of millimeter- wave applications. To fabricate the high performance GaAs-based PHEMT`s, we performed the simulation to analyze the designed epitaxial-structures. Each unit processes, such as 0.1 m$\mu$$\Gamma$-gate lithography, silicon nitride passivation and air-bridge process were developed to achieve high performance device characteristics. The DC characteristics of the PHEMT`s were measured at a 70 $\mu$m unit gate width of 2 gate fingers, and showed a good pinch-off property ($V_p$= -1.75 V) and a drain-source saturation current density ($I_{dss}$) of 450 mA/mm. Maximum extrinsic transconductance $(g_m)$ was 363.6 mS/mm at $V_{gs}$ = -0.7 V, $V_{ds}$ = 1.5 V, and $I_{ds}$ =0.5 $I_{dss}$. The RF measurements were performed in the frequency range of 1.0~50 GHz. For this measurement, the drain and gate voltage were 1.5 V and -0.7 V, respectively. At 50 GHz, 9.2 dB of maximum stable gain (MSG) and 3.2 dB of $S_{21}$ gain were obtained, respectively. A current gain cut-off frequency $(f_T)$ of 106 GHz and a maximum frequency of oscillation $(f_{max})$ of 160 GHz were achieved from the fabricated PHEMT\\`s of 0.1 m$\mu$ gate length.h.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• 복식
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• 제22권
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• pp.205-224
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• 1994

It was aimed to study the costume of Koryo dynasty based upon the thirty pictures of Bud-dha to hang on the wall among the existing Buddist paintings. The costume to study were made about 64 years during the King Chung-yol(1286) to the King Chung-jong(1350) which style was mostly related in Won Dynasty. 가) Men's wear ; 1. Hair style and hair dress ; Man tied up a top knot and they put on the hat such as a Kuan Kun and Mo. The young boys binds his hair up one, two, and three knot-s, and tied up with a hair ribbon, A kinds of Kuan-mo were Mine-lu-kuan Yuan-yu-kuan, Nong-kuan, Hae-chi-kuan Pok-du Yun-wha-kuan Yip-mo- and Tu-ku(Helmeto) 2. clothes ; 1) Colour of Koryo King's Mien-ku Kuan costume was not agree with blue and reddish black colour which was used in Yo, Song, Kum and Won Dynasty, however black and greenhish blue colour was agreed with. 2) The king wore T'ung-t'ien-kuan(Yuan-yu-kuan) and the government officials wore Chin-hien-kuan Hae-chi-kuan and Nong-kuan as a court dress. In general the king and the Crown Prince wore a hats which was used in T'ung-t'ien system however sometimes they wore small hats which was cited in literature. 3) Gate guard and upper garment wore colourful costume figured gold colour pattern which was distin-gtive costume system of Koryo. 4) A monk wore big sleeve long skirt big sleeve long jacket long skirt and shoulder scar-f full shoulder scarf or right hand shoulder opened scarf. 5) The Soldiers wore helmet shoulder or scarf pee-back hung-kap, pok-kap, yang-dan-g-kap we-yu-kap kun-kap, and boots and they carried arms. 6) The young boys wore scarf, loin cloth, long skirt, belt neckless, wan-silk, boots and foots wear and wristless. 나) Women's wear ; 1. Hair style and hairs and tied up with a hair ribbon and wore precious ston decorated hair dress wheel shape hair dress pan shaped head dress handkerchif covered hair dress decorated precious stone hair pin silk chippon made of head dress muf-fler shaped hairdress. Boots mocasin hae lee, suk and sandle wored as a shoes depends on the classes. They wore neckless, earing wres-tless and wan-pu-sik. 2. Closthe 1) High rank lade's wore un-kyun attached jacket and jacket sleeves decorated pleats and pleats decorated long skirt apron back apron knot belt, scarf this type is the same with Dang Dynasty five dynasty of china Song, Kum Won, Myung Dynasty and our cos-tume of Poe-hae, and Shilla Dynasty.