• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2006.05a
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• pp.1044-1048
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• 2006

Nuclear power generation is very dangerous in occasion that skirt of structure by earthquake although it is high effective generation that can make a lot of energies with few raw material. when design, it must consider a lot of problems caused by an earthquake. The seismic analysis of the structure has been great concern in the engineering society with an effort to reduce the severe damages from an earthquake. So the earthquake resistant design is one of the crucial design procedures of a gate valve used in nuclear power generation. The gate valve which has the contact area between stem and bellows. Because of the contact area. The gate valve should be given high stress and frictional wear. In this thesis, Considering the gate valve which has some contact distance between stem and bellows. The gate valve which has some contact distance is analyzed by a commercial FEM code of Ansys and Then compared to the gate valve behavior which doesn't have contact distance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.5
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• pp.366-370
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• 2019

In this paper, a single N+ emitter trench gate-type insulated gate bipolar transistor (IGBT) device was studied using T-CAD, in order to achieve a low on-state voltage drop (Vce-sat) and high breakdown voltage, which would reduce power loss and device reliability. Using the simulation, the threshold voltage, breakdown voltage, and on-state voltage drop were studied as a function of the temperature, the length of time in the diffusion process (drive-in) after implant, and the trench gate depth. During the drive-in process, a $20^{\circ}C$ change in temperature from 1,000 to $1,160^{\circ}C$ over a 150 minute time frame resulted in a 1 to 4 V change in the threshold voltage and a 24 to 2.6 V change in the on-state voltage drop. As a result, a 0.5 um change in the trench depth of 3.5 to 7.5 um resulted in the breakdown voltage decreasing from 802 to 692 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.27-32
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• 2003

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2070-2078
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• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.

• Journal of the Korean Magnetics Society
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• v.16 no.3
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• pp.182-185
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• 2006

In this work, we have constructed 3-axis flux-gate magnetometer for the attitude control of satellite. The constructed magnetometer shows uncertainty of ${\pm}1%$, noise level of $0.2nT/\sqrt{Hz}$ at 1 Hz under 1W power consumption. Environment test for satellite component, acceleration test and thermal cycle test were carried out. For the acceleration test, magnetometer was vibrated frequency ranging from 10 Hz to 1 kHz at 15 g (g : gravitational acceleration at earth), and for thermal cycle test, 4 times of thermal cycle were carried out temperature ranging from $-55^{\circ}C\;to\;+80^{\circ}C$ under vacuum of $1x10^{-6}Torr$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.263-267
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• 2014

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.2
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• pp.7-14
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• 1979

Design considerations of I2L are discussed with particular emphasis on the upward current gain of the npn transistor, 6J Several test structures have been fabricated to measure the DC and AC characteristics of the I2L basic cell and the base current components of the npn transistor. A T flip-flop has also been designed and fabricated using the I2L technology. The upward current gain of 10 the speed -power product of the 2.6pJ/gate and the minimum propagation delay time of 36 nsec have been obtained from the test structure. The maxmum toggle frequency of the T flip -flop has been measured to be 3.5 MHz.

• Animal cells and systems
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• v.11 no.2
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• pp.169-173
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• 2007

Hyperpolarization-activated nonselective cation channels (HCNs) play a pivotal role in producing rhythmic electrical activity in the heart and the nerve cells. In our previous experiments, voltage-dependent $Cd^{2+}$ access to one of the substituted cysteines in S6, T464C, supports the existence of an intracellular voltage-dependent activation gate. Direct binding of intracellular cAMP to HCN channels also modulates gating. Here we attempted to locate the cAMP-modulated structure that can modify the gating of HCN channels. SpHCN channels, a sea urchin homologue of the HCN family, became inactivated rapidly and intracellular cAMP removed this inactivation, resulting in about eight-fold increase of steady-state current level. T464C was probed with $Cd^{2+}$ applied to the intracellular side of the channel. We found that access of $Cd^{2+}$ to T464C was strongly gated by cAMP as well as voltage. Release of bound $Cd^{2+}$ by DMPS was also gated in a cAMP-dependent manner. Our results suggest the existence of an intracellular cAMP-modulated gate in the lower S6 region of spHCN channels.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.497-505
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• 2016

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for $0.18{\mu}m$ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.