• Journal of Power Electronics
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• v.18 no.2
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• pp.604-614
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• 2018

This paper proposes a synchronous switching technique for a Vienna rectifier that uses carrier-based pulse width modulation (CB-PWM). A three-phase Vienna rectifier, similar to a three-level T-type converter with three back-to-back switches, is used as a PWM rectifier. Conventional CB-PWM requires six independent gate signals to operate back-to-back switches. When internal switches are operated synchronously, only three independent gate signals are required, which simplifies the construction of gate driver circuits. However, with this method, total harmonic distortion of the input current is higher than that with conventional CB-PWM switching. A reactive current injection technique is proposed to improve current distortion. The performance of the proposed synchronous switching method and the effectiveness of the reactive current injection technique are verified using simulations and experiments performed with a set of Vienna rectifiers rated at 5 kW.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.245-245
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• 2008

In this work, we describe the characterization of PVP films synthesized by spin-coater method and fabricate OTFTs of a bottom gate structure using pentacene as the active layer and polyvinylphenol (PVP) as the gate dielectric on Au gate electrode. We investigated the surface and electrical properties of PVP layer using an AFM method and MIM structure, and estimated the device properties of OTFTs including $I_D-V_D$, $I_D-V_G$, threshold voltage $V_T$, on/off ratio, and field effect mobility.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.7
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• pp.70-79
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• 1996

To increase the functionality of the memories, previous studies have deifned faults models and proposed functional testing algorithms with low complexity. Although conventional testing depended strongly on functional (voltage) testing method, it couldn't detect short and open defects caused by gate oxide short and spot defect which can afect memory reliability. Therefore, IDDQ (quiescent power supply current) testing is required to detect defects and thus can obtain high reliability. In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in mOS FET and observe behavior of the memory by analyzing voltage at storge nodes of the memory and IDDQ resulting from PSPICE simulation. Finally, using this behavioral analysis, we propose a linear testing algorithm of complexity O(N) which can be applicable to both functional testing and IDDQ testing simultaneously to obtain high functionality and reliability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.497-500
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• 1999

This paper reports on the fabrication and characteristics of recessed gate GaN MESFETs fabricated using a photoelectrochemical wet etching method. The unique etching process utilizes photo-resistive mask and KOH based etchant. GaN MESFETs with successfully recessed gate structure was characterized in terms of dc and RF performance. The fabricated GaN MESFET exhibits a current saturation at $V_{DS}$ = 4 V and a pinch-off at $V_{GS}$ =-3V The peak drain current of the device is about 230mA/mm at 300 K and the value is remained almost same for 500K operation. The $f_{T}$ and $f_{max}$ from the device are 6.357Hz and 10.25 GHz, respectively.y.y.

• Journal of Information Display
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• v.13 no.4
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• pp.179-183
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• 2012

In this paper, a gate driver circuit for In-Ga-Zn-O thin-film transistors (TFTs) driven by only two clock signals is reported. In this circuit, the TFTs are turned off with a negative $V_{GS}$ by the two clock signals. As a result, it works properly and suppresses power consumption increase even though the TFT $V_T$ shifts in the negative direction.

• 전자공학회논문지 IE
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• v.44 no.2
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• pp.1-7
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• 2007

The increasing high frequency capabilities of CMOS have resulted in increased RF and analog design in CMOS. Design of RF and analog circuits depends critically on device S-parameter characteristics, magnitude of real and imaginary components and their behavior as a function of frequency. Utilization of scaled high performance CMOS technologies poses challenges as concerns for reliability degradation mechanisms increase. It is important to understand and quantify the effects of the reliability degradation mechanisms on the S-parameters and in turn on small signal model parameters. Various physical effects influencing small-signal parameters, especially the transconductance and capacitances and their degradation dependence, are discussed in detail. The measured S-parameters of H-gate and T-gate devices in a frequency range from 0.5GHz to 40GHz. All intrinsic and extrinsic parameters are extracted from S-parameters measurements at a single bias point in saturation. In this paper we discuss the analysis of the small signal equivalent circuits of RF SOI MOSFET's verificated for the purpose of exacting the change of parameter of small signal equivalent model followed by device flame.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.9-14
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• 2009

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.115-122
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• 2004

In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.383-389
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• 2001

We report on the design, fabrication, and characterization of 0.35${\mu}{\textrm}{m}$-gate AIGaAs/InGaAs PHEMTs for millimeter-wane applications. The epi-wafer structures were designed using ATLAS for optimum DC and AC characteristics, 0.351m-gate AIGaAs/rnGaAs PHEMTs having different gate widths and number of fingers were fabricated using electron beam lithography Dependence of RF characteristics of PHEMT on gate finger with and number of gate fingers have been investigated. PHEMT haying two 0.35$\times$60${\mu}{\textrm}{m}$$^2$ gate fingers showed the knee voltage, pinch-off voltage, drain saturation current density, and maximum transconductance of 1.2V, -1.5V, 275㎃/mm, and 260.17㎳/mm, respectively. The PHEMT showed fT(equation omitted)(current gain cut-off frequency) of 45㎓ and fmax(maximum oscillation frequency) of 100㎓. S$_{21}$ and MAG of the PHEMT were 3.6dB and 11.15dB, respectively, at 35㎓

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10B
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• pp.644-654
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• 2007

ZigBee is one of wireless communication standards and many applications based on Zigbee have been developing for commercial applications. Most of those applications require links to Internet like Zigbee service gateways. However, ZigBee service gateway should provides following functions to be effectively utilized itself: translation of messages between diverse ZigBee application profiles and message formats used in Internet, addition/removal of a new ZigBee service without stopping existing services according to addition/removal of a Zigbee node, and no transmission of unwanted packets to ZigBee network. Therefore, this paper proposes a new type of ZigBee Service Gateway, called ZiGate to provide the functions. The proposed ZiGate is capable of re-configurating message translation modules required in case of addition/removal of nodes and doesn't transmit unnecessary packets to the ZigBee networks by synchronizing itself with ZigBee network. And ZiGate provides translation modules between messages defined in Zigbee application profiles and both text-based and binary-based messages used in Internet. In this paper we implements the ZiGate and evaluates it on the test bed. This evaluations show that the proposed ZiGate works efficiently.