• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.476-478
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• 2006

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a $0.25{\mu}m$ CMOS process. In the design a new dynamic D-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates up to 2.5GHz and consumes 3.1mA at 2.5GHz operation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2003년도 High Temperature Superconductivity Vol.XIII
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• pp.44-44
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• 2003

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2002년도 High Temperature Superconductivity Vol.XII
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• pp.41-41
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• 2002

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
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• pp.668-671
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• 2003

A concept of deadlock point of fuzzy sequential circuit is proposed. There are six cases of fuzzy sequential circuits of 1 state and 1 input variables with deadlock points. Examples of each case are shown both in a form of characteristic equation and in a graphical illustration. As fuzzy sequential circuit with 1 state and 1 input variables, D and T fuzzy flip-Hops are also characterized using the proposed concept. Thus one of the four types of D fuzzy Hip-Hops and T fuzzy Hip-flop have a deadlock point 1/2.

• 전기전자학회논문지
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• 제19권3호
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• pp.304-310
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• 2015

SCALDO(Supercapacitor Assisted LDO) 레귤레이터는 기존에 널리 사용되고 있는 SMPS(Switch Mode Power Supply)의 장점인 높은 효율과 LDO(Low Drop-out) 레귤레이터의 장점인 안정적인 출력 및 우수한 EMI(Electro Magnetic Interference)특성을 함께 가지는 레귤레이터로 현재 새롭게 연구되고 있는 전원회로이다. 하지만, 현재까지 연구된 SCALDO 레귤레이터의 경우 회로 내부의 스위치제어에 많은 전력이 소비되어 회로 전체의 효율이 감소되는 단점이 있다. 본 논문에서는 기존 SCALDO 레귤레이터의 단점을 극복하고 저전력으로 구동이 가능한 MOSFET를 SCALDO 레귤레이터에 적용함으로써 스위치제어 소비전력을 최소화하여 회로 전체의 효율을 향상시킨 새로운 SCALDO 레귤레이터를 구현 하였으며, 기존 SCALDO 대비 효율이 최대 9.5% 상승됨을 확인하였다. 또한 기존의 MCU(Micro-controller unit)를 이용한 펌웨어제어를 비교기 및 T-F/F(Flip Flop)을 이용한 하드웨어 제어로 대체함으로써 회로의 제작과정을 단순화 하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.105-108
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• 2004

In this paper, the simple analog MPPT (Maximum Power Point Tracking) algorithm is proposed for the solar array of KOMPSAT (Korea Multi-Purpose Satellite). This method doesn't need any calculation of power by multiplication of voltage and current and a measurement of the solar array temperature. It is consist of only two sample and hold circuits, two comparators, a flip-flop, and an integrator. The proposed MPPT algorithm is verified by the simulation for the 100[W] solar array.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.48-53
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• 1999

We demonstrate small-scale high-T$_c$ superconductor RSFQ(Rapid Single Flux Quantum) circuits using multilayer bicrystal technology. An RSFQ balanced comparator is demonstrated with good current resolution, and its operating conditions are discussed in some detail. A single-loop delta-sigma modulator is realized adding a feedback loop to the comparator. The effect of the feedback is confirmed by dc measurement and simulation. A design of an RSFQ toggle flip-flop with the same multilayer bicrystal technology is suggested.

• 한국초전도ㆍ저온공학회논문지
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• 제4권1호
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• pp.17-20
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• 2002

A complex single flux quantum(SFQ) circuit could be made up of various elementary cells such as JTL(Josephson transmission line), Splitter, XOR, DC/SFQ, SFQ/DC, T flip-flop, ‥‥, etc. In this work, we have designed and simulated a SFQ circuit, which consists of DC/SFQ, JTL and SFQ/DC, based on Nb/AlO$_{x}$Nb Josephson junction technology From the simulation, we could obtain the margins for various circuit parameters. And also we have successfully operated the circuit, which was fabricated with the same design, up to the input signal frequency of about 20 GHz.z.