• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Journal of Environmental Science International
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• v.33 no.3
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• pp.217-226
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• 2024

Manufacturing workers face increased fatigue and stress due to environmental factors in workplace such as noise and vibration. Addressing this issue requires creating conducive rest spaces; however, the existing conditions of rest spaces in manufacturing workplace are subpar and lack sufficient scholarly evidence. This study investigated the effect of nature-based rest spaces on the physical and emotional recovery from fatigue on manufacturing workers. Three manufacturing complexes with nature-friendly rest spaces were selected, and 63 manufacturing workers participated in the study. The measurement tools included the Multidimensional Fatigue Scale (MFS) for fatigue levels, physiological indicators (blood pressure and heart rate), and emotional indicators (Zuckerman Inventory of Personal Reaction Scale; ZIPERS, Perceived Restorativeness Scale; PRS, Profile of Mood States; POMS and State-Trait Anxiety Inventory; STAI). The study compared recovery levels during a 7-minute rest between a space without plants and a space with natural elements. The results indicated a significant reduction in systolic and diastolic blood pressure of participants in green rest spaces compared with those in conventional rest spaces. Regarding fatigue levels, green rest spaces showed a decrease in systolic blood pressure in the middle-fatigue and high-fatigue groups. Positive feelings increased in green spaces, whereas negative emotions decreased, suggesting that short breaks in nature-friendly environments effectively promote workers' physical and emotional recovery. Furthermore, this study emphasizes the importance of green space in various work environments to promote well-being in workers.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.8
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• pp.27-35
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• 2011

In this paper, performances of the extended QRD-RLS equalizer is analyzed. Since the extended QRD-RLS equalizer is efficiently implemented by systolic array architecture, we analyze performances of this structure with signals of different lengths. By multiplying the frequency responses of the unknown channel and proposed equalizer, we observed the flatness of the overall system function. Through the simulation, it is shown that the performance of the extended QRD-RLS equalizer is remarkably increased with input signals of length 16.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.2
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• pp.43-51
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• 1997

In this paper, we quantize the image data to simplify the systolic array architecture for block matching algorithm. As the number of bits for pixel data to be processed is reduced by quantization, one can simplify the hardware of systolic array. Especially, if the bit serial input is used, one can even more simplify the structure of processing element. First, we analize the effect of quantization to a block matching. then we show the structure of quantizer and processing element when bit serial input is used. The simulation results applied to standard images have shown that the proposed block matching method has less prediction error than the conventional high speed algorithm.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.6
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• pp.749-756
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• 2015

In this paper, we propose a unique systolic structure and communication algorithm that maintains a solid link between nodes using synchronous digital communication and enables low power communication. This system was designed by using CC2500 RF transceiver, CC2590 RF front end and C8051F330 low power microcontroller. The measurement of power consumption in the network link shows below $400{\mu}W$ in data transfer rate 320bps. The system constitutes the base unit of low power wireless network that was composed of each seven link nodes having eight sensor nodes. Results of the experiments show that link nodes using a 4Ah battery could operate over 3 years without replacement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.57-64
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• 2000

In this paper, we propose the new hardware architecture which implements the stereo matching algorithm using the dynamprogrammethod. The proposed MOEPE(Merged Odd-Even PE) architecture operates in the systolic manner and finds the disparities form the intensities of the pixels on the epipolar line. The number of PEs used in the MOEPE architecture is the same number of the range constraint, which reduced the nuMber of the necessary PEs draMatically compared to the traditional method which uses the PEs with the same number of pixels on the epipolar line. For the normal sized images, the numof the MOEPE architecture is less than that of the PEs in the traditional method by 25${\times}$The proposed architecture is modeled with the VHDL code and simulated by the SYNOPSYS tool.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.1
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• pp.41-47
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• 2008

This paper presents a new digit level LSB-first multiplier for computing a modular multiplication and a modular squaring simultaneously over finite field GF($2^m$). To derive $L{\times}L$ digit level architecture when digit size is set to L, the previous algorithm is used and index transformation and merging the cell of the architecture are proposed. The proposed architecture can be utilized for the basic architecture for the crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity, and concurrency.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.373-376
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• 2001

This paper has been studied a real-time video frame data processing control that used the linear systolic array for motion estimation. The proposed data control processing provides to the input data into the multiple processor array unit(MPAU) from search area and reference block data. The proposed data control architecture has based on two slice band for input data processing. And it has no required external control logic blocks for input data as like reference block or search area data.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.293-296
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• 2001

본 논문은 GF(2$^{m}$ )상에서 파워썸 연산을 수행하는데 필요한 새로운 알고리즘과 그에 따른 병렬 입/출력 구조를 제안한다. 새로운 알고리즘은 최상위 비트 우선 구조를 기반으로 하고, 제안된 구조는 기존의 구조에 비해 낮은 하드웨어 복잡도와 적은 지연을 가진다. 이는 역원과 나눗셈 연산을 위한 기본 구조로 사용될 수 있으며 암호 프로세서 칩 디자인의 기본 구조로 이용될 수 있고, 또한 단순성, 규칙성과 병렬성으로 인해 VLSI 구현에 적합하다.