• International Journal of Contents
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• 제9권1호
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• 한국멀티미디어학회논문지
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• 제14권10호
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• pp.1275-1286
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• 2011

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

• 한국통신학회논문지
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• 제14권5호
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• pp.442-452
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• 1989

시스토릭 어레이를 이용한 FIR 필터를 구현하여 고속처리가 가능하게 설계하였으며, Cascade하게 칩연결이 가능하도록 설계하여 최대 128차의 FIR 필터를 실현할 수 있도록 하였다. 필터 계수는 Sign and Magnitude 형태로 외부에서 입력하며, 데이터는 2's Complement 형태로 입력되게 시스템을 설계하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.787-790
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• 2003

This paper describes a high speed correlator that can acquire synchronization quickly. The existing addition algorithm is a binary adder tree architecture that will result in extremely slow speed of operation due to many levels of logic required for computation of correlation[2][3]. This paper suggests the new various architectures, which are systolic array architecture, simple pipeline architecture and block systolic array architecture[4][5]. The acquisition performance of the proposed architectures is analyzed and compared with the existing architecture. The comparison results show that the systolic array architecture and the block systolic array architecture reduce the timing delay up to 73% and 31%, respectively. And the results show that the simple pipeline architecture reduces the timing delay up to 53%..

• 전자공학회논문지A
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• 제33A권2호
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• pp.163-172
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• 1996

In reconfiguration of systolic arrays, a potential disadvantage is that in the PRESENCE of consective faulty PE's logically connected PE's may be far apart, requiring the reduction of clock speed and thus reducing throughput of the array. Thus it is fundamental tokeep locality of interconnections as high as possible even after reconfiguration and to make reconfiguration implemented in the simple routing devices. However requirements of locality and simplicity mean that reconfiguring capability is limited. This paper deals iwth the issue of developing efficient method for reconfiguration of 2-D systolic arrays which can be achieved high reconfiguration rate, with the two conditions satisfying using concept of pseudo faulty processing element. Applying this concept to reconfiguration of systolic array, we have found similar condition. The simulation shows that recomfiguration rates are 97%, 84% when N faults ocurs on the N$\times$N array n case of N=5, 8 respectively.

• 전자공학회논문지C
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• 제34C권10호
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• 한국컴퓨터정보학회논문지
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• 제3권4호
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• pp.55-62
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• 1998

이 논문은 수치해석에서 적분값을 구하는데 이용되는 Romberg 적분법이 많은 계산량으로 인하여 소프트웨어적인 방법으로는 처리 속도가 떨어지므로 수치처리를 위한 툴 키트를 사용시 처리속도가 떨어진다. 그래서 이 논문에서는 시스토릭어레이를 이용하여 Romberg 적분법에 적분값을 구하는 새로운 하드웨어를 제안하였다. 이 새로운 하드웨어는Romberg 적분법이 2단계로 나누어져있어서 2단계의 시스토릭어레이로 설계를 하였다. 첫번째 단계는 사다리꼴 적분법에 의해서 근사치를 구하고, 두 번째는 단계는 구해진 적분값을수렴속도도 빠르고 근사 값을 정확하게 하기 위해서 오차의 위수를 높여 가는 방법에 많이사용하는 Richardson의 외삽법을 적용하여 적분값을 구하는 것이다.

• 지능정보연구
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• 제6권1호
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• pp.113-128
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• 2000

This paper presents a first year report of an ongoing multi-year project to develop a systolic parallel simulation system for dynamic traffic assignment. The fundamental approach to the simulation is systolic parallel processing based on autonomous agent modeling. Agents continuously act on their own initiatives and access to database to get the status of the simulation world. Various agents are defined in order to populate the simulation world. In particular existing modls and algorithm were incorporated in designing the behavior of relevant agents such as car-following model headway distribution Frank-Wolf algorithm and so on. Simulation is based on predetermined routes between centroids that are computed off-line by a conventional optimal path-finding algorithm. Iterating the cycles of optimization-then-simulation the proposed system will provide a realistic and valuable traffic assignment. Gangnum-Gu district in Seoul is selected for the target are for the modeling. It is expected that realtime traffic assignment services can be provided on the internet within 3 years.

• 디지털산업정보학회논문지
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• 제18권1호
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.