• Proceedings of the KSRS Conference
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• 2004.10a
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• pp.220-223
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• 2004

Automatic image registration is an essential element of remote sensing because remote sensing system generates enormous amount of data, which are multiple observations of the same features at different times and by different sensor. The general process of automatic image registration includes three steps: 1) The extraction of features to be used in the matching process, 2) the feature matching strategy and accurate matching process, 3) the resampling of the data based on the correspondence computed from matched feature. For step 2) and 3), we have developed an algorithms for automated registration of satellite images with RANSAC(Random Sample Consensus) in success. However, for step 1), There still remains human operation to generate GCP Chips, which is time consuming, laborious and expensive process. The main idea of this research is that we are able to automatically generate GCP chips with comer detection algorithms without GPS survey and human interventions if we have systematic corrected satellite image within adaptable positional accuracy. In this research, we use SUSAN(Smallest Univalue Segment Assimilating Nucleus) algorithm in order to detect the comer. SUSAN algorithm is known as the best robust algorithms for comer detection in the field of compute vision. However, there are so many comers in high-resolution images so that we need to reduce the comer points from SUSAN algorithms to overcome redundancy. In experiment, we automatically generate GCP chips from IKONOS images with geo level using SUSAN algorithms. Then we extract reference coordinate from IKONOS images and DEM data and filter the comer points using texture analysis. At last, we apply automatically collected GCP chips by proposed method and the GCP by operator to in-house automatic precision correction algorithms. The compared result will be presented to show the GCP quality.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.1
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• pp.7-15
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• 2002

This paper is concerned with remote environment monitoring & control for the breeding house as scattering far and wide. The environment data is detected in the breeding house that is collected to one processor. It's adapted to the PSTN(public switch tele-phone network) and multi-processing for exchange the environment data and the control data in between the manager and a breeding house by micro-processor. We have designed the algorithm of the communication sequence through the experimental research. This system is composed of sensor interface, FSK communications, LED display, data latch and MCS-51 single-chip. The S/W is composed with data acquisition by multi-processing, data communication and interrupt. And this paper is Proposed the DB structure algorithm concern to a mount scale using web design. The subject is a performance of effective management for the breeding house.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.17 no.5
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• pp.128-134
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• 2018

In this paper, two ports feeding a microstrip patch antenna using a quadrature hybrid circuit was proposed to enhance the bandwidth for the global positioning system(GPS). The square patch was designed, and the probe feeding was applied. The quadrature hybrid chip circuit for two-port feeding was designed, and output ports that have a 90-degree phase difference feed to the patch antenna. The designed patch and quadrature hybrid circuit were implemented on an FR4 board, and were combined. The measurement of the bandwidth within a voltage standing wave ratio(VSWR) of 2:1 and axial ratio(AR) in 3dB were wide band as 29% BW (1,230~1,700 MHz) and 15.87% BW (1,400~1,650 MHz), respectively. Antenna gain were measured 2.75dBi at the center frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.1-7
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• 2012

A 9b MS/s CMOS cyclic folding A/D converter (ADC) for intelligent battery sensor and battery management systems is proposed. The proposed ADC structure is based on a cyclic architecture to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolating structure. The prototype ADC implemented with a 0.35um 2P4M n-well CMOS process shows a measured INL and DNL of maximum 1.5LSB and 1.0LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 110mW at 2MS/s and 3.3V. The occupied active die area is $10mm^2$.

• Parasites, Hosts and Diseases
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• v.49 no.4
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• pp.341-347
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• 2011

Acanthamoeba infection is difficult to treat because of the resistance property of Acanthamoeba cyst against the host immune system, diverse antibiotics, and therapeutic agents. To identify encystation mediating factors of Acanthamoeba, we compared the transcription profile between cysts and trophozoites using microarray analysis. The DNA chip was composed of 12,544 genes based on expressed sequence tag (EST) from an Acanthamoeba ESTs database (DB) constructed in our laboratory, genetic information of Acanthamoeba from TBest DB, and all of Acanthamoeba related genes registered in the NCBI. Microarray analysis indicated that 701 genes showed higher expression than 2 folds in cysts than in trophozoites, and 859 genes were less expressed in cysts than in trophozoites. The results of real-time PCR analysis of randomly selected 9 genes of which expression was increased during cyst formation were coincided well with the microarray results. Eukaryotic orthologous groups (KOG) analysis showed an increment in T article (signal transduction mechanisms) and O article (posttranslational modification, protein turnover, and chaperones) whereas significant decrement of C article (energy production and conversion) during cyst formation. Especially, cystein proteinases showed high expression changes (282 folds) with significant increases in real-time PCR, suggesting a pivotal role of this proteinase in the cyst formation of Acanthamoeba. The present study provides important clues for the identification and characterization of encystation mediating factors of Acanthamoeba.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.65-75
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• 2011

As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

• The Journal of Engineering Research
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• v.3 no.1
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• pp.97-106
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• 1998

In this paper, we analyze the WLL systems with high chip rate, which virtually eliminates the multipath fading effects by appling space diversity functions. First, we found out the capacity of reverse link which resulted from performing computer simulation of the transmission and reception of the WLL systems to evaluate the performance of the WLL systems in real environment. Besides, we analyze the radio propagation medium and the link budget and from the results, made RCSU for providing of the AWGN multipath fading channel. This RCSU is produced to characterize the urban radio propagation medium in various environments. From the simulation results, diversity gains increase as depth of fading becomes deeper. We also confirm that the systems applied diversity reduce the effects of multipath fading phenomena which cause to degrade the performance of WLL systems, based on the results $E_b/N_o$ and BER curve.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.12
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• pp.61-68
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• 2004

Wireless mobile communication systems request high speed mobility and high speed data transmission capability. In order to meet the requirements, OFDM(Orthogonal Frequency Division Multiplex) is mainly adopted in the physical layer of the wireless systems. In commercial wireless mobile systems, IEEE802.(11a, 16e, etc) series seem to be used as the modulation method. For supporting multiple air-interfaces in a wireless mobile system, different kinds of OFDM based modulation methods should be supported in one modem chip. It requires a variable point IFFT/FFT or reconfigurable IFFT/FFT processor. In this paper, we propose the design method of a reconfigurable IFFT/FFT processor. In addition, it is shown that a reconfigurable IFFT/FFT processor can he implemented by using the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.