• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.20-25
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• 2010

An integrated Mach-Zehnder interferometric sensor operating at 632.8 nm was designed and fabricated by the technology of planar rib waveguides. Rib waveguide based on silica system ($SiO_2-SiO_xN_y-SiO_2$) was geometrically designed to have single mode operation and high sensitivity. It was structured by semiconductor fabrication processes such as thin film deposition, photolithography, and RIE (Reactive Ion Etching). With the power observation, propagation loss measurement by cut-back method showed about 4.82 dB/cm for rib waveguides. Additionally the chromium mask process for an etch stop was employed to solve the core damaging problem in patterning the sensing zone on the chip. Refractive index measurement of water/ethanol mixture with this device finally showed a sensitivity of about $\pi$/($4.04{\times}10^{-3}$).

• Korean Journal of Optics and Photonics
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• v.14 no.1
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• pp.97-102
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• 2003

Multi-channel images of 11-MUA(11-Mercaptoundecanoic acid) and 11-MUOH(11-Mercaptoundecanol) self-assembled monolayers were obtained by using two-dimensional surface plasmon resonance (SPR) absorption. The patterning process was simplified by exploiting direct photo-oxidation of thiol bonding (photolysis) instead of conventional photolithography. Sharper images were resolved by using a white light source in combination with a narrow bandpass filter in the visible region, minimizing the diffraction patterns on the images. The line profile calibration of the image contrast caused by different resonance conditions at each point on the sensor surface (at a fixed incident angle) enables us to discriminate the monolayer thickness in nanometer scale. Furthermore, there is no signal degradation such as photo bleaching or quenching, which are common in the detection methods based on fluorescence.

• Korean Journal of Materials Research
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• v.5 no.7
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• pp.794-801
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• 1995

To connect the driver IC and Al coated glass, a method has been developed to plate electrolessly Ni on Al/PR system. It Is necessary to pretreat Al to remove oxide film before plating. In order to find pretreatment process which does not damage photoresist or glass, alkaline and fluoride zincate process have been investigated. Because photoresist and aluminum thin film can easily dissolve in alkaline solution, it is considered that the fluoride zincate process was a suitable one. After immersion in the zincate solution containing 1.5 g/$\ell$ ammonium bifluoride and 100 g/$\ell$ zinc sulfate, electroless nickel plating could be performed. The additive in the zincate solution and thiourea in the plating solution increased smoothness of the plated surface. Acld dip could improve the uniformit of the surface.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.10
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• pp.65-72
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• 1998

The BTA drilling chip is better for deep hole drilling than other self-piloting with pad drilling chips because the large length to diameter ratio allows a unique cutting force dispersion and better supplies the high pressure fluid. Therefore the BTA is useful for many tasks, such as coolant hole drilling of large scale dies, as well as tube seat drilling, which is essential for the heat exchanger, and variable component drilling for automobiles. Deep hole drilling has several significant problems, such as hole deviation, hole over-size, circularity, straightness, and surface roughness. The reasons for these problems, which often result in quality short comings, are an alignment of the BTA drilling system and the unbalance of cutting force by work piece and tool shape. This paper analyzes the properties through an experiment which com¬pared single-edge BTA drills with multiple-edge BTA drills, as well as the shapes of the tools to cause an unbalance of cutting force, and its effect on the precision of the worked hole. Conclusions are as follows. 1) In SMSSC drilling, 60m/min of BTA with single and multi-edged tools proved the best cutting condition and the lowest wear character. 2) The roundness got a little worse as cutting speed was increased, but surface roughness was hot affected. 3) It was proved that the burnishing torque of both drills approached 26%. which is almost the same as the 24% insisted on by Griffiths, and the dispersion characteristic of the multi-edged BTA drill proved better than the single-edge BTA drill.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.118-118
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• 2008

The oxide CMP has been applied to interlayer dielectric(ILD) and shallow trench isolation (STI) in chip fabrication. Recently the slurry used in oxide CMP being changed from silica slurry to ceria (cerium dioxide) slurry particularly in STI CMP, because the material selectivity of ceria slurry is better than material selectivity of silica slurry. Moreover, the ceria slurry has good a planarization efficiency, compared with silica slurry. However ceria abrasives make a material removal rate too high at the region of wafer center. Then we focuses on why profile of material removal rate is convex. The material removal rate sharply increased to 3216 $\AA$/min by $4^{th}$ run without conditioning. After $4^{th}$ run, material removal rate converged. Furthermore, profile became more convex during 12 run. And average material removal rate decreased when conditioning process is added to end of CMP process. This is due to polishing mechanism of ceria. Then the ceria abrasive remains at the pad, in particular remains more at wafer center contacted region of pad. The field emission scanning electron microscopy (FE-SEM) images showed that the pad sample in the wafer center region has a more ceria abrasive than in wafer outer region. The energy dispersive X-ray spectrometer (EDX) verified the result that ceria abrasive is deposited and more at the region of wafer center. Therefore, this result may be expected as ceria abrasives on pad surface causing the convex profile of material removal rate.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.101-110
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• 2006

One of the most effective ways to improve cache performance is to exploit both temporal and spatial locality given by any program executional characteristics. This paper proposes a data cache with small space for low power but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block sire and a fully-associative buffer with large block size. To overcome the disadvantage of small cache space, two mechanisms are enhanced by considering operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes and an efficient block filtering to remove rarely reused data. The simulations on MediaBench show that the proposed 5KB-cache can provide equivalent performance and reduce energy consumption up to 40% as compared with 16KB 4-way set associative cache.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.1-8
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• 2002

Most of the traditional embedded web server systems have been designed for monitoring and controlling some dedicated equipments. Hence, not only they have no generality and flexibility but also they are too expensive for the lower-cost domestic equipment. To cope with these difficulty, we suggest a lower-cost ${\mu}$-embedded web server model which is suitable for monitoring and controlling the industry or house equipments by using the internet. The suggested model is based on an one-chip ${\mu}$-processor in which the ISP (In-System Programming) function and flash ROM are embedded basically to minimize the cost of H/W and S/W. Also it allows to add an new function dynamically to provide the generality and flexibility. Finally, to evaluate the feasibility of the suggested model, we have manufactured a test-board based on the ATMega103 ${\mu}$-processor and programmed the control program and tested it on the MS Explorer 5.0 environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.11
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• pp.1470-1476
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• 2020

This paper describes a design of a lightweight security system-on-chip (SoC) suitable for the implementation of security protocols for IoT and mobile devices. The security SoC using Cortex-M0 as a CPU integrates hardware crypto engines including an elliptic curve cryptography (ECC) core, a SHA3 hash core, an ARIA-AES block cipher core and a true random number generator (TRNG) core. The ECC core was designed to support twenty elliptic curves over both prime field and binary field defined in the SEC2, and was based on a word-based Montgomery multiplier in which the partial product generations/additions and modular reductions are processed in a sub-pipelining manner. The H/W-S/W co-operation for elliptic curve digital signature algorithm (EC-DSA) protocol was demonstrated by implementing the security SoC on a Cyclone-5 FPGA device. The security SoC, synthesized with a 65-nm CMOS cell library, occupies 193,312 gate equivalents (GEs) and 84 kbytes of RAM.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.