• Title/Summary/Keyword: System-on-chip

Search Result 1,737, Processing Time 0.03 seconds

The Implementation of Remote Meter Reading System Using Bluetooth Technology & SkT3 Protocol in CDMA (블루투스와 CDMA의 SMS프로토콜을 이용한 원격 가스 검침 시스템의 구현)

  • 김종현;김영길
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2003.05a
    • /
    • pp.443-446
    • /
    • 2003
  • This paper implement Remote Meter Reading System which is used Bluetooth and SMS in CDMA. This System propose system which tan detect a total amount of gas, electricity or water without a meterman, at home BlueTooth is a close range wireless communication technology which uses a wireless frequency 2.4GHz and has a high trust and self error correction technology according to a low power consumption quality and a high-speed frequency hopping. This makes get a high trust concerning a data transmission than an existing modem. In addition, though wireless modem is restricted by a minimal of a wireless terminal, it will be possible to coincide with the function of the portable with the low power consumption quality by using Bluetooth. And as the system on a chip of module progresses, the possibility of the small size is present. Nowadays, SMS Protocol in CDMA for have a network function based on PPP in CDMA Phone. The proposed Remote Meter Reading System to get more nobility, efficiency, and have good function. SMS Protocol in CDMA have profits which is low power, low cost, and low microwave output.

  • PDF

TEST DB: The intelligent data management system for Toxicogenomics (독성유전체학 연구를 위한 지능적 데이터 관리 시스템)

  • Lee, Wan-Seon;Jeon, Ki-Seon;Um, Chan-Hwi;Hwang, Seung-Young;Jung, Jin-Wook;Kim, Seung-Jun;Kang, Kyung-Sun;Park, Joon-Suk;Hwang, Jae-Woong;Kang, Jong-Soo;Lee, Gyoung-Jae;Chon, Kum-Jin;Kim, Yang-Suk
    • Proceedings of the Korean Society for Bioinformatics Conference
    • /
    • 2003.10a
    • /
    • pp.66-72
    • /
    • 2003
  • Toxicogenomics is now emerging as one of the most important genomics application because the toxicity test based on gene expression profiles is expected more precise and efficient than current histopathological approach in pre-clinical phase. One of the challenging points in Toxicogenomics is the construction of intelligent database management system which can deal with very heterogeneous and complex data from many different experimental and information sources. Here we present a new Toxicogenomics database developed as a part of 'Toxicogenomics for Efficient Safety Test (TEST) project'. The TEST database is especially focused on the connectivity of heterogeneous data and intelligent query system which enables users to get inspiration from the complex data sets. The database deals with four kinds of information; compound information, histopathological information, gene expression information, and annotation information. Currently, TEST database has Toxicogenomics information fer 12 molecules with 4 efficacy classes; anti cancer, antibiotic, hypotension, and gastric ulcer. Users can easily access all kinds of detailed information about there compounds and simultaneously, users can also check the confidence of retrieved information by browsing the quality of experimental data and toxicity grade of gene generated from our toxicology annotation system. Intelligent query system is designed for multiple comparisons of experimental data because the comparison of experimental data according to histopathological toxicity, compounds, efficacy, and individual variation is crucial to find common genetic characteristics .Our presented system can be a good information source for the study of toxicology mechanism in the genome-wide level and also can be utilized fur the design of toxicity test chip.

  • PDF

Implementation of a Predictor for Cell Phase Monitoring at the OLT in the ATM-PON (ATM-PON의 OLT에서 상향 셀 위상감시를 위한 예측기의 구현)

  • Mun, Sang-Cheol;Chung, Hae;Kim, Woon-Ha
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.27 no.2C
    • /
    • pp.160-169
    • /
    • 2002
  • An ATM-PON (Passive Optical Network) system consists of an OLT (Optical Line Termination), multiple ONUs (Optical Network Units) and the optical fiber which has a PON (Passive Optical Network)configuration with a passive optical splitter. To avoid cell collisions on the upstream transmission, an elaborate procedure called as ranging is needed when a new ONU is installed. The ONU can send upstream cells according to the grant provided by the OLT after the procedure. To prevent collisions being generated by the variation of several factors, OLT must performs continuously the cell phase monitoring. It means that the OLT predicts the expected arrival time, monitors the actual arrival time for all upstream cells and calculates the error between the times. Accordingly, TC (Transmission Convergence) chip in the OLT needs a predictor which predicts the time that the cell will arrive for the current grant. In this paper, we implement the predictor by using shift registers of which the length is equivalent to the equalized round trip delay. As each register consists of 8 bit, OLT can identify which ONU sends what type of cell (ranging cell, user cell, idle cell, and mini-slot). Also, TC chip is designed to calculate the effective bandwidth for all ONUs by using the function of predictor. With the time simulation and the measurement of an implemented optical board, we verify the operation of the predictor.

An 8b 240 MS/s 1.36 ㎟ 104 mW 0.18 um CMOS ADC for High-Performance Display Applications (고성능 디스플레이 응용을 위한 8b 240 MS/s 1.36 ㎟ 104 mW 0.18 um CMOS ADC)

  • In Kyung-Hoon;Kim Se-Won;Cho Young-Jae;Moon Kyoung-Jun;Jee Yong;Lee Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.42 no.1
    • /
    • pp.47-55
    • /
    • 2005
  • This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

Design of Real-Time PreProcessor for Image Enhancement of CMOS Image Sensor (CMOS 이미지 센서의 영상 개선을 위한 실시간 전처리 프로세서의 설계)

  • Jung, Yun-Ho;Lee, Joon-Hwan;Kim, Jae-Seok;Lim, Won-Bae;Hur, Bong-Soo;Kang, Moon-Gi
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.38 no.8
    • /
    • pp.62-71
    • /
    • 2001
  • This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.

  • PDF

Transcriptome Profiling of Kidney Tissue from FGS/kist Mice, the Korean Animal Model of Focal Segmental Glomerulosclerosis (국소성 분절성 사구체 신병증의 동물 모델 (FGS/kist 생쥐) 신 조직의 유전자 발현 양상)

  • Kang, Hee-Gyung;Lee, Byong-Sop;Lee, Chul-Ho;Ha, Il-Soo;Cheong, Hae-Il;Choi, Yong
    • Childhood Kidney Diseases
    • /
    • v.15 no.1
    • /
    • pp.38-48
    • /
    • 2011
  • Purpose: Focal segmental glomerulosclerosis (FSGS) is the most common glomerulopathy causing pediatric renal failure. Since specific treatment targeting the etiology and pathophysiology of primary FSGS is yet elusive, the authors explored the pathophysiology of FSGS by transcriptome analysis of the disease using an animal model. Methods: FGS/kist strain, a mouse model of primary FSGS, and RFM/kist strain, as control and the parent strain of FGS/kist, were used. Kidney tissues were harvested and isolated renal cortex was used to extract mRNA, which was run on AB 1700 mouse microarray chip after reverse transcription to get the transcriptome profile. Results: Sixty two genes were differentially expressed in FGS/kist kidney tissue compared to the control. Those genes were related to cell cycle/cell death, immune reaction, and lipid metabolism/vasculopathy, and the key molecules of their networks were TNF, IL-6/4, IFN${\gamma}$, TP53, and PPAR${\gamma}$. Conclusion: This study confirmed that renal cell death, immune system activation with subsequent fibrosis, and lipid metabolism-related early vasculopathy were involved in the pathophysiology of FSGS. In addition, the relevance of methodology used in this study, namely transcriptome profiling, and Korean animal model of FGS/kist was validated. Further study would reveal novel pathophysiology of FSGS for new therapeutic targets.

Design and Implementation of 8b/10b Encoder/Decoder for Serial ATA (직렬 ATA용 8b/10b 인코더와 디코더 설계 및 구현)

  • Heo Jung-Hwa;Park Nho-Kyung;Park Sang-Bong
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.29 no.1A
    • /
    • pp.93-98
    • /
    • 2004
  • Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

An Effective Mitigation Method on the Signal-Integrity Effects by Splitting of a Return Current Plane (귀환 전류 평면의 분할에 기인하는 신호 무결성의 효과적인 대책 방법)

  • Jung, Ki-Bum;Jun, Chang-Han;Chung, Yeon-Choon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.19 no.3
    • /
    • pp.366-375
    • /
    • 2008
  • Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each sub system, this partition will cause unwanted effects. In a circuital point of view, RCP partition has a bad influence upon signal integrity. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is usecl for the way of maintaining signal integrity, still specific user's guide doesn't give sufficient principle. In a view point of signal integrity, design principle of multi-CB using method will be analyzed by measurement and simulation. And design principle of noise mitigation will be provided. Generally interval of CB is ${\lambda}/20$ ferrite bead. In this study. When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement and simulation. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of signal integrity.

A 0.31pJ/conv-step 13b 100MS/s 0.13um CMOS ADC for 3G Communication Systems (3G 통신 시스템 응용을 위한 0.31pJ/conv-step의 13비트 100MS/s 0.13um CMOS A/D 변환기)

  • Lee, Dong-Suk;Lee, Myung-Hwan;Kwon, Yi-Gi;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.46 no.3
    • /
    • pp.75-85
    • /
    • 2009
  • This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

System on Chip Policy of Major Nations (주요국의 시스템반도체 정책 및 시사점)

  • Chun, Hwang-Soo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2012.05a
    • /
    • pp.747-749
    • /
    • 2012
  • This paper is analyzing the SoC policy of major nations as the U.S, Japan, Europe, Taiwan, China and draw the suggestions for the development of semiconductor industry in Korea. SoC is the non-memory semiconductor to support and put into action the function of system. SoC is big market over the 200billion dollars and have a huge potential for new IT convergence market. Developed countries as the US, Japan, and Europe have enforced the industrial competitiveness by company investment and Taiwan supported the SoC Industry by government fund. Korea is No.1 superpower in DRAM semiconductor, but very weak in SoC Industry. We should secure the competitiveness of SoC Industry by the development of core technology, planning the growth policy, and building the cooperative model to leap the SoC power nation.

  • PDF