• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.10a
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• pp.276-280
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• 2001

In the development of Chip Mounter(C/M), much interests have risen regarding how to decrease the operation time of mounting the different chips on the printed circuit board(PCB). The existing method to determine the time sequence of teaching C/M was to follow the procedure which was made by the operater. IN this study, a new but effective algorithm has been developed and employed in SCM-130 Chip Mounter and its online programming had reduced the mounting time significantly and provided the basis for the future online CAD/CAM system.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.309-310
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• 2006

FPGA와 DSP기술을 이용한 여러 변복조방식을 통합하는 다기능 System-On-Chip 보드 개발하여 기존의 아날로그 방식에 비해 확장의 용이성 및 시간 인력의 절감을 가져오며, 향후 디지털 통신 실험 장치에 대한 기술력 확보등을 목표로 하고 있다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04d
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• pp.286-288
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• 2003

본 논문에서는 서로 다른 네트워크간의 다양한 프로토콜과 이종의 트래픽을 동시에 처리할 수 있는 네트워크용 SoC (System-on-a-Chip) 프로세서를 구현하였다. 제작된 네트워크 SoC 프로세서는 ARM 프로세서 코어와 ATM(Asynchronous Transfer Mode) 블록, 10/100 Mbps 이더넷 볼록, 스케쥴러, UART 등을 이용하였고 각 블록은 AM8A (Advanced Microcontroller Bus Architecture) 버스로 연결하였다. SoC 프로세서는 CADENCE사의 VerilogHDL을 이용하여 설계하였고 0.35$\mu\textrm{m}$ 셀 라이브러리를 이용하여 검증하였다. 구현된 칩은 총 게이트수가 312,000개이며 칠의 최대 동작 주파수는 50MHz 이다.

• ETRI Journal
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• v.30 no.6
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• pp.783-789
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• 2008

A bio-inspired vision chip for edge detection was fabricated using 0.35 ${\mu}m$ double-poly four-metal complementary metal-oxide-semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of $160{\times}120$ pixels has been fabricated in $5{\times}5\;mm^2$ silicon die. It shows less than 10 mW of power consumption.

• 한국생물공학회:학술대회논문집
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• 2005.04a
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• pp.18-18
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• 2005

Photoinduced electron transport process in nature such as photoelectric conversion and long-range electron transfer in photosynthetic organisms are known to occur not only very efficiently but also unidirectionally through the functional groups of biomolecules. The basic principles in the development of new functional devices can be inspired from the biological systems such as molecular recognition, electron transfer chain, or photosynthetic reaction center. By mimicking the organization of the biological system, molecular electronic devices can be realized $artificially^{1)}$. The nano-fabrication technology of biomolecules was applied to the development of nano-protein chip for simultaneously analyzing many kinds of proteins as a rapid tool for proteome research. The results showed that the self-assembled protein layer had an influence on the sensitivity of the fabricated bio-surface to the target molecules, which would give us a way to fabricate the nano-protein chip with high sensitivity. The results implicate that the biosurface fabrication using self-assembled protein molecules could be successfully applied to the construction of nanoscale bio-photodiode and nano-protein chip based on electrical detection.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.86-92
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• 2011

In this paper, we propose a novel hardware MPI(Message Passing Interface) unit which supports message passing in multiprocessor system which use distributed memory architecture. MPI Hardware unit processes data synchronization, transmission and completion, and it supports processor non-blocking operation so it reduces overhead according to synchronization. Additionally, MPI hardware unit combines ready entry, request entry, reserve entry which save and manage the synchronized messages and performs the multiple outstanding issue and out of order completion. According to BFM(Bus Functional Model) simulation result, the performance is increased by 25% on many to many communication. After we designed MPI unit using HDL, with synopsys design compiler we synthesized, and for synthesis library we used MagnaChip $0.18{\mu}m$. And then we making prototype chip. The proposed message transmission interface hardware shows high performance for its increase in size. Thus, as we consider low-cost design and scalability, MPI hardware unit is useful in increasing overall performance of embedded MPSoC(Multi-Processor System-on-Chip).

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2040-2042
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• 2004

This paper presents a miniature optical system for the fluorescence detection of the patterned protein chip. The patterned protein chip was fabricated using MEMS process. The fluorescence from the patterned protein chip was measured while varying the concentration of the BSA. The fluorescence light is separated spatially from the excitation beam using mini-size prism to increase SNR (Signal-to-Noise Ratio). The combination of prism and mirrors can convert the excitation light from the laser diode to uniform illumination on the specimen. We believe that the proposed system for fluorescence detection can be applied to rea1ization of point-of-care.