• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.795-805
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• 2012

This paper proposes an algorithm and a hardware architecture for a broadcast communication which has the worst bottleneck among multiprocessor using distributed memory architectures. In conventional system, The pipelined broadcast algorithm is an algorithm which takes advantage of maximum bandwidth of communication bus. But unnecessary synchronization process are repeated, because the pipelined broadcast sends the data divided into many parts. In this paper, the MPI unit for pipeline chain algorithm based on circuit switching removing the redundancy of synchronization process was designed, the proposed architecture was evaluated by modeling it with systemC. Consequently, the performance of the proposed architecture was highly improved for broadcast communication up to 3.3 times that of systems using conventional pipelined broadcast algorithm, it can almost take advantage of the maximum bandwidth of transmission bus. Then, it was implemented with VerilogHDL, synthesized with TSMC 0.18um library and implemented into a chip. The area of synthesis results occupied 4,700 gates(2 input NAND gate) and utilization of total area is 2.4%. The proposed architecture achieves improvement in total performance of MPSoC occupying relatively small area.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.201-207
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• 2008

This paper presents the implementation of a Tiling System about Preprocessing functions of JPEG 2000. The system covers the JPEG 2000 standard and is designed to determine the size of the image, to expand the image area and to split input image into several tiles. In order to split the input image with the progressive transmission into several tiles and transmit a tile of this image to others, this system store this image into Frame Memory. Therefore, this is designed as the Finite State Machine (FSM) to sequence through specific patterns of states in a predetermined sequential manner by using Verilog-HDL and be designed to handle a maximum 5M image. Moreover, for identifying image size for expansion, we propose several formula which are based on remainder after division (rem). we propose the true table which determines the size of the image input patterns by using results of these formula. Under the condition of TSMC 0.25um ASIC library, gate count is 18,725 and maximum data arrival time is 18.94 [ns].

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.17-22
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• 2009

FlexRay is a new standard of network communication system which provides solutions to the degradation problems generated by many ECU (Electronic Control Unit) connections in automobiles and automation systems. The upper bound of the data rate is 10Mbps and it provides two channels for redundancy In this paper, FlexRay system is first designed using SDL. For hardware implementation, FlexRay system is designed using Verilog HDL based on the SDL design result. The designed system is synthesized using Synopsys Design Compiler with the Magna/Hynix 0.18 um cell library. In this paper, to construct a FlexRay network, active star is used since active star systems can provide high speed data transmission up to 10Mbps. The performance of the star network is tested using one transmitter node and two receiver nodes.

• Journal of IKEEE
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• v.24 no.3
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• pp.783-790
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• 2020

In this paper, the human detecting radar system for indoor security applications is proposed, and its FPGA-based implementation results are presented. In order to minimize the complexity and memory requirements of the computation, the top half of the spectrogram was used to extract features, excluding the feature extraction techniques that require complex computation, feature extraction techniques were proposed considering classification performance and complexity. In addition, memory requirements were minimized by designing a pipeline structure without storing the entire spectrogram. Experiments on human, dog and robot cleaners were conducted for classification, and 96.2% accuracy performance was confirmed. The proposed system was implemented using Verilog-HDL, and we confirmed that a low-area design using 1140 logics and 6.5 Kb of memory was possible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.24-30
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• 2010

In this paper, we described intra prediction which is the one of techniques to be used for higher compression performance in H.264/AVC and proposed the design of intra predictor for efficient intra prediction mode processing. The proposed system is consist of processing elements, precomputation processing elements, an intra prediction controller, an internal memory and a register controller. The proposed system needs the reduced the computation cycles by using processing elements and precomputation processing element and also needs the reduced the number of access time to external memory by using internal memory and registers architecture. We designed the proposed system with Verilog-HDL and verified with suitable test vectors which are encoded YUV files. The proposed architecture belongs to the baseline profile of H.264/AVC decoder and is suitable for portable devices such as cellular phone with the size of $176{\times}144$. As a result of experiment, the performance of the proposed intra predictor is about 60% higher than that of the previous one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2443-2450
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• 2014

In the motion recognition system using depth image, the depth image is converted to the real world formed 3D point cloud data for efficient algorithm apply. And then, output depth image is converted by the projective world after algorithm apply. However, when coordinate conversion, rounding error and data loss by applied algorithm are occurred. In this paper, when convert 3D point cloud data to depth image, we proposed efficient conversion method and its hardware implementation without rounding error and data loss according image size change. The proposed system make progress using the OpenCV and the window program, and we test a system using the Kinect in real time. In addition, designed using Verilog-HDL and verified through the Zynq-7000 FPGA Board of Xilinx.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.4
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• pp.371-376
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• 2004

Distributed Network Protocol Version 3.0 (DNP3.0) is the communication protocol developed for the interoperability between a RTU and a central control station of SCADA in the power utility industry. In this paper DNP3.0 is implemented by using HDL with FPGA and C program on Hitachi H8/532 processor. DNP3.0 is implemented from physical layer to network layer in hardware level to reduce the computing load on a CPU. Finally, the ASIC for DNP3.0 has been manufactured from Hynix Semiconductor. The commercial feasibility of the hardware through the communication test with ASE2000 and DNP Master Simulator is performed. The developed protocol becomes one of IP, and can be used to implement SoC for the terminal device in SCADA systems. Also, the result can be applicable to various industrial controllers because it is implemented in HDL.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.175-178
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• 2009

H.264/AVC is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. In this paper, we explained Intra Prediction in H.264/AVC, which is able to achieve higher compressing efficiency from correlation removal of adjacent samples in spatial domain, and proposed efficient Intra Predictor architecture design for H.264/AVC decoder. The proposed system reduced computation cycle using processing element and precomputation processing element and also reduced the number of access to external memory using efficient register. We designed the proposed system with Verilog-HDL and verified with suitable test vector. The proposed Intra Predictor achieved about 60% cycle reduction comparing with existing Intra Predictors.