• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.155-162
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• 2010

To ensure accurate measurements of wireless network performance, it should be collected real-time data which are transmitted between a large number of nodes in the actual network environment. Therefore, it is necessary to develop simulation tool for finding optimal network system design method such as media access control, routing technique, ad-hoc algorithm of node deployment while overcoming spatial and temporal constraints. Our research attempts to provide an improved architecture and design method of simulation tool for wireless network is an application of multi-threading technique in these issues. We finally show that usability of the proposed simulator by comparing results derived from same test environment in the wireless LAN model of our simulator and widely used network simulation package, NS-2.

• Smart Structures and Systems
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• v.18 no.1
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• pp.75-92
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• 2016

The design of a semi-active (SA) control system addressed to mitigate wind induced structural demand to high wind turbine towers is discussed herein. Actually, the remarkable growth in height of wind turbines in the last decades, for a higher production of electricity, makes this issue pressing than ever. The main objective is limiting bending moment demand by relaxing the base restraint, without increasing the top displacement, so reducing the incidence of harmful "p-delta" effects. A variable restraint at the base, able to modify in real time its mechanical properties according to the instantaneous response of the tower, is proposed. It is made of a smooth hinge with additional elastic stiffness and variable damping respectively given by springs and SA magnetorheological (MR) dampers installed in parallel. The idea has been physically realized at the Denmark Technical University where a 1/20 scale model of a real, one hundred meters tall wind turbine has been assumed as case study for shaking table tests. A special control algorithm has been purposely designed to drive MR dampers. Starting from the results of preliminary laboratory tests, a finite element model of such structure has been calibrated so as to develop several numerical simulations addressed to calibrate the controller, i.e., to achieve as much as possible different, even conflicting, structural goals. The results are definitely encouraging, since the best configuration of the controller leaded to about 80% of reduction of base stress, as well as to about 30% of reduction of top displacement in respect to the fixed base case.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.30 no.2
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• pp.127-135
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• 2017

The computing environment has changed rapidly to enable large-scale finite element models to be analyzed at the PC or workstation level, such as multi-core CPU, optimal math kernel library implementing BLAS and LAPACK, and popularization of direct sparse solvers. In this paper, the design considerations on a parallel finite element code for shared memory based multi-core CPU system are proposed; (1) the use of optimized numerical libraries, (2) the use of latest direct sparse solvers, (3) parallelism using OpenMP for computing element stiffness matrices, and (4) assembly techniques using triplets, which is a type of sparse matrix storage. In addition, the parallelization effect is examined on the time-consuming works through a large scale finite element model.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.1-10
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• 2008

In this paper, we designed a facial feature(eyes, a moult and a nose) detection hardware based on the ICT transform which was developed for face detection earlier. Our design used a pipeline architecture for high throughput and it also tried to reduce memory size and memory access rate. The algerian and its hardware implementation were tested on the BioID database, which is a worldwide face detection test bed, and its facial feature detection rate was 100% both in software and hardware, assuming the face boundary was correctly detected. After synthesizing the hardware on Dongbu $0.18{\mu}m$ CMOS library, its die size was $376,821{\mu}m^2$ with the maximum operating clock 78MHz.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.1-11
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Journal of the Korean Ceramic Society
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• v.40 no.3
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• pp.286-292
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• 2003

In this study, new shock absorbing system was proposed using silica gel particles according to the nano-technology. For the design and real application of the proposed damper, an experimental investigations are carried out using colloidal damper, which is statically loaded. The porous matrix is composed from silica gel(labyrinth architecture), coated by organo-silicones substances, in order to achieve a hydrophobic surface. Water is considered as associated lyophobic liquid. Reversible colloidal damper static test rig and the measuring technique of the static hysteresis were described. Iufluence of the water volume and particle diameters upon the reversible colloidal damper hysteresis was investigated. Also, influence of the relaxation time on the hysteresis of the damper was investigated. As a result, the proposed new shock absorbing damper is proved as an effective one, which can be replaced for the conventional hydraulic damper.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.711-720
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• 2001

An enlarging a scale of logical domain organizing Internet, security policy association among entities become complicated. Establishment and control of security policies for each system is a hard problem to solve because of the environment and composite factors with variable properties. In this paper, to solve this actual problems, we orgainze a hierarchical structure of network and than we design the structure of database to apply security policies for secure communication. This enables efficient management of security data and association of security policy by using designed data structure between different domain in hierarchical structure with make secure communication possible.

• Journal of Korean Society of Steel Construction
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• v.25 no.2
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• pp.179-186
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• 2013

Steel braced frames are commonly used because braced frames are one of the most economical and efficient seismic resisting systems. However, research into the behavior of multi-story X-braced frame systems with mid-span gusset plates, as used in practice, is limited. As a result, their seismic performance and the influence of connection design on this performance are not well understood. Detailed nonlinear computer analyses of the frame were performed prior to building the test specimens and were used to aid the design and to predict the system performance. These analyses suggested significantly different behavior for the midspan gusset plate than that noted for the corner gusset plate connections. This paper summarizes the results of a full scale, 2-story braced frame analysis and test on concentrically braced frames.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.687-694
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• 2008

Given the daily tactical schedule, the purpose of the traffic management system is to develop operating plan that will achieve the stated schedule as best as possible. The operating plan has to be modified during the day because of occurring disturbance(e.g. delay, infrastructure breakdown, etc.) Conflict detection and resolution(CDRS) are aimed for adjusting the distorted schedule to tactical schedule. Our research separate CDRS into two hierarchy modules, line conflict control module and station conflict control module. We define the role of each modules and design the cooperative architecture. We suggest the conflict detection and resolution approach based on mathematical model. These results can be implemented as prototype modules.